diff options
| author |   Ido Barnea <ibarnea@cisco.com> | 2016-07-19 10:12:20 +0300 |
|---|---|---|
| committer | Ido Barnea <ibarnea@cisco.com> | 2016-07-24 14:01:11 +0300 |
| commit | 8b0119ed99f893106a560ccb9db31c99e1d293eb (patch) | |
| tree | 7e3eb6ef214af20fa975f28779a28479bfd73d5a /src/dpdk/drivers/net/i40e/i40e_fdir.c | |
| parent | 3c106ce73a4a54863ed1c3df47c09eb1e63fadaf (diff) | |
dpdk0716 move:DPDK file patches
Diffstat (limited to 'src/dpdk/drivers/net/i40e/i40e_fdir.c')
| -rw-r--r-- | src/dpdk/drivers/net/i40e/i40e_fdir.c | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/src/dpdk/drivers/net/i40e/i40e_fdir.c b/src/dpdk/drivers/net/i40e/i40e_fdir.c index f65c4110..4f9a6b48 100644 --- a/src/dpdk/drivers/net/i40e/i40e_fdir.c +++ b/src/dpdk/drivers/net/i40e/i40e_fdir.c @@ -74,8 +74,11 @@ #define I40E_FDIR_UDP_DEFAULT_LEN 400 /* Wait count and interval for fdir filter programming */ -#define I40E_FDIR_WAIT_COUNT 10 -#define I40E_FDIR_WAIT_INTERVAL_US 1000 +#define TREX_PATCH +// TREX_PATCH - Values were 10 and 1000. These numbers give much better performance when +// configuring large amount of rules +#define I40E_FDIR_WAIT_COUNT 100 +#define I40E_FDIR_WAIT_INTERVAL_US 100 /* Wait count and interval for fdir filter flush */ #define I40E_FDIR_FLUSH_RETRY 50 @@ -729,6 +732,9 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input, fdir_input->flow.ip4_flow.ttl : I40E_FDIR_IP_DEFAULT_TTL; ip->type_of_service = fdir_input->flow.ip4_flow.tos; +#ifdef TREX_PATCH + ip->packet_id = rte_cpu_to_be_16(fdir_input->flow.ip4_flow.ip_id); +#endif /* * The source and destination fields in the transmitted packet * need to be presented in a reversed order with respect @@ -1143,8 +1149,11 @@ i40e_fdir_filter_programming(struct i40e_pf *pf, fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK); fdirdp->dtype_cmd_cntindex |= - rte_cpu_to_le_32( - ((uint32_t)pf->fdir.match_counter_index << +#ifdef TREX_PATCH + rte_cpu_to_le_32((fdir_action->stat_count_index << +#else + rte_cpu_to_le_32((pf->fdir.match_counter_index << +#endif I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & I40E_TXD_FLTR_QW1_CNTINDEX_MASK); @@ -1168,11 +1177,17 @@ i40e_fdir_filter_programming(struct i40e_pf *pf, I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) { +#ifndef TREX_PATCH + /* itay: moved this delay after the check to avoid first check */ rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US); +#endif if ((txdp->cmd_type_offset_bsz & rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) == rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) break; +#ifdef TREX_PATCH + rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US); +#endif } if (i >= I40E_FDIR_WAIT_COUNT) { PMD_DRV_LOG(ERR, "Failed to program FDIR filter:" @@ -1180,7 +1195,10 @@ i40e_fdir_filter_programming(struct i40e_pf *pf, return -ETIMEDOUT; } /* totally delay 10 ms to check programming status*/ +#ifndef TREX_PATCH + /* itay: tests show this is not needed */ rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US); +#endif if (i40e_check_fdir_programming_status(rxq) < 0) { PMD_DRV_LOG(ERR, "Failed to program FDIR filter:" " programming status reported."); |