Our patches to dpdk1702 - not including mlx changes

Signed-off-by: Ido Barnea <ibarnea@cisco.com>

3 files changed, 157 insertions, 14 deletions

diff --git a/src/dpdk/drivers/net/i40e/i40e_ethdev.c b/src/dpdk/drivers/net/i40e/i40e_ethdev.c
index 4492bcc1..f8ee5a60 100644
--- a/src/dpdk/drivers/net/i40e/i40e_ethdev.c
+++ b/src/dpdk/drivers/net/i40e/i40e_ethdev.c
@@ -704,6 +704,9 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 
 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 
+#define TREX_PATCH
+#define TREX_PATCH_LOW_LATENCY
+
 /*
  * Add a ethertype filter to drop all flow control frames transmitted
  * from VSIs.
@@ -2515,9 +2518,11 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
 			    I40E_GLPRT_PTC9522L(hw->port),
 			    pf->offset_loaded, &os->tx_size_big,
 			    &ns->tx_size_big);
+#ifndef TREX_PATCH
 	i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
 			   pf->offset_loaded,
 			   &os->fd_sb_match, &ns->fd_sb_match);
+#endif
 	/* GLPRT_MSPDC not supported */
 	/* GLPRT_XEC not supported */
 
@@ -2543,10 +2548,17 @@ i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 			pf->main_vsi->eth_stats.rx_multicast +
 			pf->main_vsi->eth_stats.rx_broadcast -
 			pf->main_vsi->eth_stats.rx_discards;
+#ifndef TREX_PATCH
 	stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
 			pf->main_vsi->eth_stats.tx_multicast +
 			pf->main_vsi->eth_stats.tx_broadcast;
 	stats->ibytes   = ns->eth.rx_bytes;
+#else
+    /* Hanoch: move to global transmit and not pf->vsi and we have two high and low priorty */
+    stats->opackets = ns->eth.tx_unicast +ns->eth.tx_multicast +ns->eth.tx_broadcast;
+	stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
+#endif
+
 	stats->obytes   = ns->eth.tx_bytes;
 	stats->oerrors  = ns->eth.tx_errors +
 			pf->main_vsi->eth_stats.tx_errors;
@@ -4327,10 +4339,18 @@ i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
 	/* create floating veb if vsi is NULL */
 	if (vsi != NULL) {
 		ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
-				      I40E_DEFAULT_TCMAP, false,
+#ifdef TREX_PATCH_LOW_LATENCY
+                      vsi->enabled_tc, false,
+#else
+                      I40E_DEFAULT_TCMAP, false,
+#endif
 				      &veb->seid, false, NULL);
 	} else {
+#ifdef TREX_PATCH_LOW_LATENCY
+		ret = i40e_aq_add_veb(hw, 0, 0, vsi->enabled_tc,
+#else
 		ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
+#endif
 				      true, &veb->seid, false, NULL);
 	}
 
@@ -4489,6 +4509,57 @@ i40e_update_default_filter_setting(struct i40e_vsi *vsi)
 	return i40e_vsi_add_mac(vsi, &filter);
 }
 
+#ifdef TREX_PATCH_LOW_LATENCY
+static int
+i40e_vsi_update_tc_max_bw(struct i40e_vsi *vsi, u16 credit){
+    struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
+    int ret;
+
+    if (!vsi->seid) {
+        PMD_DRV_LOG(ERR, "seid not valid");
+        return -EINVAL;
+    }
+
+    ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, credit,0, NULL);
+    if (ret != I40E_SUCCESS) {
+        PMD_DRV_LOG(ERR, "Failed to configure TC BW");
+        return ret;
+    }
+    return (0);
+}
+
+static int
+i40e_vsi_update_tc_bandwidth_ex(struct i40e_vsi *vsi)
+{
+	struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
+	int i, ret;
+    struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw_data;
+    struct i40e_aqc_configure_vsi_tc_bw_data * res_buffer;
+
+	if (!vsi->seid) {
+		PMD_DRV_LOG(ERR, "seid not valid");
+		return -EINVAL;
+	}
+
+	memset(&tc_bw_data, 0, sizeof(tc_bw_data));
+	tc_bw_data.tc_valid_bits = 3;
+
+    /* enable TC 0,1 */
+	ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw_data, NULL);
+	if (ret != I40E_SUCCESS) {
+		PMD_DRV_LOG(ERR, "Failed to configure TC BW");
+		return ret;
+	}
+    
+    vsi->enabled_tc=3;
+    res_buffer = ( struct i40e_aqc_configure_vsi_tc_bw_data *)&tc_bw_data;
+    (void)rte_memcpy(vsi->info.qs_handle, res_buffer->qs_handles,
+					sizeof(vsi->info.qs_handle));
+
+	return I40E_SUCCESS;
+}
+#endif
+
 /*
  * i40e_vsi_get_bw_config - Query VSI BW Information
  * @vsi: the VSI to be queried
@@ -4565,7 +4636,8 @@ i40e_enable_pf_lb(struct i40e_pf *pf)
 
 	/* Use the FW API if FW >= v5.0 */
 	if (hw->aq.fw_maj_ver < 5) {
-		PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
+        //TREX_PATCH - changed from ERR to INFO. Most of our customers do not have latest FW
+		PMD_INIT_LOG(INFO, "FW < v5.0, cannot enable loopback");
 		return;
 	}
 
@@ -9831,6 +9903,7 @@ i40e_dcb_hw_configure(struct i40e_pf *pf,
  *
  * Returns 0 on success, negative value on failure
  */
+//TREX_PATCH - changed all ERR to INFO in below func
 static int
 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
 {
@@ -9839,7 +9912,7 @@ i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
 	int ret = 0;
 
 	if ((pf->flags & I40E_FLAG_DCB) == 0) {
-		PMD_INIT_LOG(ERR, "HW doesn't support DCB");
+		PMD_INIT_LOG(INFO, "HW doesn't support DCB");
 		return -ENOTSUP;
 	}
 
@@ -9861,8 +9934,12 @@ i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
 			hw->local_dcbx_config.etscfg.willing = 0;
 			hw->local_dcbx_config.etscfg.maxtcs = 0;
 			hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
-			hw->local_dcbx_config.etscfg.tsatable[0] =
-						I40E_IEEE_TSA_ETS;
+			hw->local_dcbx_config.etscfg.tsatable[0] = I40E_IEEE_TSA_ETS;
+#ifdef TREX_PATCH_LOW_LATENCY
+            hw->local_dcbx_config.etscfg.tcbwtable[1] = 0;
+            hw->local_dcbx_config.etscfg.tsatable[1] = I40E_IEEE_TSA_STRICT;
+            hw->local_dcbx_config.etscfg.prioritytable[1] = 1;
+#endif
 			hw->local_dcbx_config.etsrec =
 				hw->local_dcbx_config.etscfg;
 			hw->local_dcbx_config.pfc.willing = 0;
@@ -9877,13 +9954,20 @@ i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
 						I40E_APP_PROTOID_FCOE;
 			ret = i40e_set_dcb_config(hw);
 			if (ret) {
-				PMD_INIT_LOG(ERR,
+				PMD_INIT_LOG(INFO,
 					"default dcb config fails. err = %d, aq_err = %d.",
 					ret, hw->aq.asq_last_status);
 				return -ENOSYS;
 			}
+#ifdef TREX_PATCH_LOW_LATENCY
+            if (i40e_vsi_update_tc_bandwidth_ex(pf->main_vsi) !=
+                I40E_SUCCESS) {
+                PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
+                return -ENOSYS;
+            }
+#endif
 		} else {
-			PMD_INIT_LOG(ERR,
+			PMD_INIT_LOG(INFO,
 				"DCB initialization in FW fails, err = %d, aq_err = %d.",
 				ret, hw->aq.asq_last_status);
 			return -ENOTSUP;
@@ -9896,12 +9980,12 @@ i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
 		ret = i40e_init_dcb(hw);
 		if (!ret) {
 			if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
-				PMD_INIT_LOG(ERR,
+				PMD_INIT_LOG(INFO,
 					"HW doesn't support DCBX offload.");
 				return -ENOTSUP;
 			}
 		} else {
-			PMD_INIT_LOG(ERR,
+			PMD_INIT_LOG(INFO,
 				"DCBX configuration failed, err = %d, aq_err = %d.",
 				ret, hw->aq.asq_last_status);
 			return -ENOTSUP;
diff --git a/src/dpdk/drivers/net/i40e/i40e_fdir.c b/src/dpdk/drivers/net/i40e/i40e_fdir.c
index 0700253b..eddb2b9f 100644
--- a/src/dpdk/drivers/net/i40e/i40e_fdir.c
+++ b/src/dpdk/drivers/net/i40e/i40e_fdir.c
@@ -74,8 +74,11 @@
 #define I40E_FDIR_UDP_DEFAULT_LEN           400
 
 /* Wait count and interval for fdir filter programming */
-#define I40E_FDIR_WAIT_COUNT       10
-#define I40E_FDIR_WAIT_INTERVAL_US 1000
+#define TREX_PATCH
+// TREX_PATCH - Values were 10 and 1000. These numbers give much better performance when
+// configuring large amount of rules
+#define I40E_FDIR_WAIT_COUNT       100
+#define I40E_FDIR_WAIT_INTERVAL_US 100
 
 /* Wait count and interval for fdir filter flush */
 #define I40E_FDIR_FLUSH_RETRY       50
@@ -751,6 +754,9 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 					fdir_input->flow.ip4_flow.ttl :
 					I40E_FDIR_IP_DEFAULT_TTL;
 		ip->type_of_service = fdir_input->flow.ip4_flow.tos;
+#ifdef TREX_PATCH
+        ip->packet_id = rte_cpu_to_be_16(fdir_input->flow.ip4_flow.ip_id);
+#endif
 		/*
 		 * The source and destination fields in the transmitted packet
 		 * need to be presented in a reversed order with respect
@@ -771,7 +777,11 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 		ip6->vtc_flow =
 			rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 					 (fdir_input->flow.ipv6_flow.tc <<
-					  I40E_FDIR_IPv6_TC_OFFSET));
+					  I40E_FDIR_IPv6_TC_OFFSET)
+#ifdef TREX_PATCH
+                             | (fdir_input->flow.ipv6_flow.flow_label & 0x000fffff)
+#endif
+                             );
 		ip6->payload_len =
 			rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 		ip6->proto = fdir_input->flow.ipv6_flow.proto ?
@@ -1272,8 +1282,12 @@ i40e_fdir_filter_programming(struct i40e_pf *pf,
 	fdirdp->dtype_cmd_cntindex |=
 			rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
 	fdirdp->dtype_cmd_cntindex |=
+#ifdef TREX_PATCH
+			rte_cpu_to_le_32((fdir_action->stat_count_index <<
+#else
 			rte_cpu_to_le_32(
 			((uint32_t)pf->fdir.match_counter_index <<
+#endif
 			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 			I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
 
@@ -1297,11 +1311,17 @@ i40e_fdir_filter_programming(struct i40e_pf *pf,
 	I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 
 	for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
+#ifndef TREX_PATCH
+        /* itay: moved this delay after the check to avoid first check */
 		rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
+#endif
 		if ((txdp->cmd_type_offset_bsz &
 				rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
 				rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
 			break;
+#ifdef TREX_PATCH
+        rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
+#endif
 	}
 	if (i >= I40E_FDIR_WAIT_COUNT) {
 		PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
@@ -1309,7 +1329,10 @@ i40e_fdir_filter_programming(struct i40e_pf *pf,
 		return -ETIMEDOUT;
 	}
 	/* totally delay 10 ms to check programming status*/
+#ifndef TREX_PATCH
+    /* itay: tests show this is not needed */
 	rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
+#endif
 	if (i40e_check_fdir_programming_status(rxq) < 0) {
 		PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
 			    " programming status reported.");
diff --git a/src/dpdk/drivers/net/i40e/i40e_rxtx.c b/src/dpdk/drivers/net/i40e/i40e_rxtx.c
index 608685fa..8aa55eef 100644
--- a/src/dpdk/drivers/net/i40e/i40e_rxtx.c
+++ b/src/dpdk/drivers/net/i40e/i40e_rxtx.c
@@ -1708,12 +1708,21 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
 	uint16_t base, bsf, tc_mapping;
 	int use_def_burst_func = 1;
 
+#define TREX_PATCH_LOW_LATENCY
+#ifdef TREX_PATCH_LOW_LATENCY
+    int is_vf = 0;
+#endif
+
 	if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
 		struct i40e_vf *vf =
 			I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 		vsi = &vf->vsi;
-	} else
+#ifdef TREX_PATCH_LOW_LATENCY
+        is_vf = 1;
+#endif
+	} else {
 		vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
+    }
 
 	if (vsi == NULL) {
 		PMD_DRV_LOG(ERR, "VSI not available or queue "
@@ -1829,6 +1838,12 @@ i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
 		ad->rx_bulk_alloc_allowed = false;
 	}
 
+#ifdef TREX_PATCH_LOW_LATENCY
+    if (! is_vf)
+        rxq->dcb_tc =0;
+    else // The entire for below is in the else
+#endif
+
 	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
 		if (!(vsi->enabled_tc & (1 << i)))
 			continue;
@@ -1936,12 +1951,24 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
 	uint16_t tx_rs_thresh, tx_free_thresh;
 	uint16_t i, base, bsf, tc_mapping;
 
+#ifdef TREX_PATCH_LOW_LATENCY
+    u8 low_latency = 0;
+    int is_vf = 1;
+#endif
+
 	if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
 		struct i40e_vf *vf =
 			I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 		vsi = &vf->vsi;
-	} else
+	} else {
 		vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
+#ifdef TREX_PATCH_LOW_LATENCY
+        if (queue_idx == pf->dev_data->nb_tx_queues-1) {
+            low_latency = 1;
+        }
+        is_vf = 0;
+#endif
+    }
 
 	if (vsi == NULL) {
 		PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
@@ -2096,6 +2123,15 @@ i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
 	/* Use a simple TX queue without offloads or multi segs if possible */
 	i40e_set_tx_function_flag(dev, txq);
 
+#ifdef TREX_PATCH_LOW_LATENCY
+    if (! is_vf) {
+        if (low_latency) {
+            txq->dcb_tc=1;
+        }else{
+            txq->dcb_tc=0;
+        }
+    } else // The entire for below is in the else
+#endif
 	for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
 		if (!(vsi->enabled_tc & (1 << i)))
 			continue;