diff options
| author |   Ido Barnea <ibarnea@cisco.com> | 2016-10-05 16:18:39 +0300 |
|---|---|---|
| committer | Ido Barnea <ibarnea@cisco.com> | 2016-10-05 16:22:51 +0300 |
| commit | d62aeaa718739812c82e34e95405f3b640d76093 (patch) | |
| tree | 71b9f6cb6bc41f553069d22e154732cb4311409f /src | |
| parent | efb8873783d59ae2e5a870a99f05e40ebf661c16 (diff) | |
Fix issue with set_rcv_all in 1G
Diffstat (limited to 'src')
| -rw-r--r-- | src/main_dpdk.cpp | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/src/main_dpdk.cpp b/src/main_dpdk.cpp index edeeb3ee..480045f5 100644 --- a/src/main_dpdk.cpp +++ b/src/main_dpdk.cpp @@ -5543,16 +5543,17 @@ int CTRexExtendedDriverBase1G::set_rcv_all(CPhyEthIF * _if, bool set_on) { clear_rx_filter_rules(_if); - if (! set_on) - return 0; - - for (int rule_id = 0; rule_id < sizeof(eth_types); rule_id++) { - mask |= 0x1 << rule_id; - // Filter for byte 12 of packet - _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 4) , 0x000000 | eth_types[rule_id]); - _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 8) , 0x10); /* MASK */ - // FLEX_PRIO[[18:16] = 1, RQUEUE[10:8] = 1, len = 24 - _if->pci_reg_write( (E1000_FHFT(rule_id) + 0xFC) , (1 << 16) | (1 << 8) | 24); + if (set_on) { + for (int rule_id = 0; rule_id < sizeof(eth_types); rule_id++) { + mask |= 0x1 << rule_id; + // Filter for byte 12 of packet + _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 4) , 0x000000 | eth_types[rule_id]); + _if->pci_reg_write( (E1000_FHFT(rule_id)+(1*16) + 8) , 0x10); /* MASK */ + // FLEX_PRIO[[18:16] = 1, RQUEUE[10:8] = 1, len = 24 + _if->pci_reg_write( (E1000_FHFT(rule_id) + 0xFC) , (1 << 16) | (1 << 8) | 24); + } + } else { + configure_rx_filter_rules(_if); } return 0; |