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-rw-r--r--scripts/automation/regression/stateless_tests/stl_rx_test.py4
-rw-r--r--scripts/stl/burst_simple.py36
2 files changed, 38 insertions, 2 deletions
diff --git a/scripts/automation/regression/stateless_tests/stl_rx_test.py b/scripts/automation/regression/stateless_tests/stl_rx_test.py
index 36f17170..16029908 100644
--- a/scripts/automation/regression/stateless_tests/stl_rx_test.py
+++ b/scripts/automation/regression/stateless_tests/stl_rx_test.py
@@ -428,7 +428,7 @@ class STLRX_Test(CStlGeneral_Test):
self.check_stats (stats,ls['tx_pkts'][pid], pkts,"ls['tx_pkts'][pid]")
self.check_stats (stats,ls['tx_bytes']['total'], tbytes,"ls['tx_bytes']['total']")
- self.check_stats (stats,ls['tx_bytes'][pid], pkts+1,"ls['tx_bytes'][pid]")
+ self.check_stats (stats,ls['tx_bytes'][pid], tbytes,"ls['tx_bytes'][pid]")
return 0
@@ -448,7 +448,7 @@ class STLRX_Test(CStlGeneral_Test):
for port in all_ports:
for l in [True,False]:
print(" test port {0} latency : {1} ".format(port,l))
- self.send_1_burst(port,False,100)
+ self.send_1_burst(port,l,100)
# this test adds more and more latency streams and re-test with incremental
diff --git a/scripts/stl/burst_simple.py b/scripts/stl/burst_simple.py
new file mode 100644
index 00000000..87d7a5a1
--- /dev/null
+++ b/scripts/stl/burst_simple.py
@@ -0,0 +1,36 @@
+from trex_stl_lib.api import *
+
+class STLS1(object):
+
+ def __init__ (self):
+ self.fsize =64; # the size of the packet
+
+
+ def create_stream (self):
+
+ # Create base packet and pad it to size
+ size = self.fsize - 4; # HW will add 4 bytes ethernet FCS
+ base_pkt = Ether(dst="00:00:00:00:00:01")/IP(src="16.0.0.1",dst="48.0.0.1")/UDP(dport=12,sport=1025)
+ pad = max(0, size - len(base_pkt)) * 'x'
+
+
+ return STLProfile( [ STLStream( isg = 1.0, # start in delay in usec
+ packet = STLPktBuilder(pkt = base_pkt/pad),
+ mode = STLTXSingleBurst( pps = 1000),
+ )
+
+ ]).get_streams()
+
+
+ def get_streams (self, direction = 0, **kwargs):
+ # create 1 stream
+ return self.create_stream()
+
+
+# dynamic load - used for trex console or simulator
+def register():
+ return STLS1()
+
+
+
+