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-rw-r--r--scripts/automation/regression/functional_tests/stl_basic_tests.py3
-rw-r--r--scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py26
-rwxr-xr-xscripts/automation/trex_control_plane/stl/trex_stl_lib/utils/parsing_opts.py1
-rw-r--r--scripts/stl/tests/multi_core_test.py6
4 files changed, 15 insertions, 21 deletions
diff --git a/scripts/automation/regression/functional_tests/stl_basic_tests.py b/scripts/automation/regression/functional_tests/stl_basic_tests.py
index 28178324..bc5bc4d5 100644
--- a/scripts/automation/regression/functional_tests/stl_basic_tests.py
+++ b/scripts/automation/regression/functional_tests/stl_basic_tests.py
@@ -340,11 +340,13 @@ class CStlBasic_Test(functional_general_test.CGeneralFunctional_Test):
seed = time.time()
# test with simple vars
+ print(format_text("\nTesting multiple flow vars for multicore\n", 'underline'))
rc = self.run_sim('stl/tests/multi_core_test.py', output = None, options = '--test_multi_core --limit=840 -t test_type=plain#seed={0} -m 27kpps'.format(seed), silent = True)
assert_equal(rc, True)
# test with tuple
+ print(format_text("\nTesting multiple tuple generators for multicore\n", 'underline'))
rc = self.run_sim('stl/tests/multi_core_test.py', output = None, options = '--test_multi_core --limit=840 -t test_type=tuple#seed={0} -m 27kpps'.format(seed), silent = True)
assert_equal(rc, True)
@@ -356,6 +358,7 @@ class CStlBasic_Test(functional_general_test.CGeneralFunctional_Test):
]
for mc_test in mc_tests:
+ print(format_text("\ntesting {0} for multicore...\n".format(mc_test), 'underline'))
rc = self.run_sim(mc_test, output = None, options = '--test_multi_core --limit=840 -m 27kpps', silent = True)
assert_equal(rc, True)
diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
index 63a1232b..54ec2da9 100644
--- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
+++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/trex_stl_sim.py
@@ -558,25 +558,13 @@ def test_multi_core (r, options):
print("")
- print(format_text("comparing 2 cores to 1 core:\n", 'underline'))
- rc = compare_caps_strict('1.cap', '2.cap')
- if rc:
- print("[Passed]\n")
-
- print(format_text("comparing 4 cores to 1 core:\n", 'underline'))
- rc = compare_caps('1.cap', '4.cap')
- if rc:
- print("[Passed]\n")
-
- print(format_text("comparing 6 cores to 1 core:\n", 'underline'))
- rc = compare_caps('1.cap', '6.cap')
- if rc:
- print("[Passed]\n")
-
- print(format_text("comparing 8 cores to 1 core:\n", 'underline'))
- rc = compare_caps('1.cap', '8.cap')
- if rc:
- print("[Passed]\n")
+ for core_count in range(1, 9):
+ print(format_text("comparing {0} cores to 1 core:\n".format(core_count), 'underline'))
+ rc = compare_caps_strict('1.cap', '{0}.cap'.format(core_count))
+ if rc:
+ print("[Passed]\n")
+
+ return
def main (args = None):
diff --git a/scripts/automation/trex_control_plane/stl/trex_stl_lib/utils/parsing_opts.py b/scripts/automation/trex_control_plane/stl/trex_stl_lib/utils/parsing_opts.py
index 65333e0f..b42b56af 100755
--- a/scripts/automation/trex_control_plane/stl/trex_stl_lib/utils/parsing_opts.py
+++ b/scripts/automation/trex_control_plane/stl/trex_stl_lib/utils/parsing_opts.py
@@ -222,7 +222,6 @@ def decode_tunables (tunable_str):
# each token is of form X=Y
for token in tokens:
- print(token)
m = re.search('(.*)=(.*)', token)
if not m:
raise argparse.ArgumentTypeError("bad syntax for tunables: {0}".format(token))
diff --git a/scripts/stl/tests/multi_core_test.py b/scripts/stl/tests/multi_core_test.py
index 918a30bf..ccb66cb8 100644
--- a/scripts/stl/tests/multi_core_test.py
+++ b/scripts/stl/tests/multi_core_test.py
@@ -68,9 +68,13 @@ class STLMultiCore(object):
port_min = rng.randint(0, port_bound - 1)
port_max = rng.randint(port_min, port_bound - 1)
+ # 840 is the least common multiple
+ limit_flows = 840 * rng.randint(1, 1000)
vm += [STLVmTupleGen(ip_min = ip_min, ip_max = ip_max,
port_min = port_min, port_max = port_max,
- name = name),
+ name = name,
+ limit_flows = limit_flows),
+
STLVmWrFlowVar (fv_name = name + ".ip", pkt_offset = pkt_offset ), # write ip to packet IP.src]
STLVmWrFlowVar (fv_name = name + ".port", pkt_offset = (pkt_offset + 4) ),
]