diff options
Diffstat (limited to 'src/dpdk22/drivers/net')
-rw-r--r-- | src/dpdk22/drivers/net/i40e/i40e_ethdev.c | 34 | ||||
-rw-r--r-- | src/dpdk22/drivers/net/i40e/i40e_fdir.c | 9 |
2 files changed, 39 insertions, 4 deletions
diff --git a/src/dpdk22/drivers/net/i40e/i40e_ethdev.c b/src/dpdk22/drivers/net/i40e/i40e_ethdev.c index 0a1e9efc..510a98cd 100644 --- a/src/dpdk22/drivers/net/i40e/i40e_ethdev.c +++ b/src/dpdk22/drivers/net/i40e/i40e_ethdev.c @@ -695,6 +695,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) #define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8)) +// 0 - statfull mode. 1 stateless. +static int trex_mode=0; +void i40e_set_trex_mode(int mode) { + trex_mode = mode; +} + static void i40e_dump_filter_regs(struct i40e_hw *hw) { int reg_nums[] = {31, 33, 34, 35, 41, 43}; @@ -716,9 +722,7 @@ static inline void i40e_filter_fields_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_GLQF_ORT(12), 0x00000062); I40E_WRITE_REG(hw, I40E_GLQF_PIT(2), 0x000024A0); I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(31, 0), 0); - I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(31, 1), 0x00040000); I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(33, 0), 0); - I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(33, 1), 0x00040000); I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(41, 0), 0); I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(41, 1), 0x00080000); I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(43, 0), 0); @@ -727,7 +731,15 @@ static inline void i40e_filter_fields_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(34, 1), 0x00040000); // filter IP according to ttl and L4 protocol I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 0), 0); - I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 1), 0x00040000); + if (trex_mode == 1) { + I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 1), 0x00100000); + I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(31, 1), 0x00100000); + I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(33, 1), 0x00100000); + } else { + I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(35, 1), 0x00040000); + I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(31, 1), 0x00040000); + I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(33, 1), 0x00040000); + } I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(44, 0), 0); I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(44, 1), 0x00080000); I40E_WRITE_REG(hw, I40E_GLQF_FD_MSK(0, 34), 0x000DFF00); @@ -2059,9 +2071,12 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) I40E_GLPRT_PTC9522L(hw->port), pf->offset_loaded, &os->tx_size_big, &ns->tx_size_big); +#ifndef TREX_PATCH i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index), pf->offset_loaded, &os->fd_sb_match, &ns->fd_sb_match); +#endif + /* GLPRT_MSPDC not supported */ /* GLPRT_XEC not supported */ @@ -2084,6 +2099,19 @@ i40e_trex_get_speed(struct rte_eth_dev *dev) } } +//TREX_PATCH +// fill stats array with fdir rules match count statistics +void +i40e_trex_fdir_stats_get(struct rte_eth_dev *dev, uint32_t *stats, uint32_t start, uint32_t len) +{ + int i; + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + for (i = 0; i < len; i++) { + stats[i] = I40E_READ_REG(hw, I40E_GLQF_PCNT(i + start)); + } +} + /* Get all statistics of a port */ static void i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) diff --git a/src/dpdk22/drivers/net/i40e/i40e_fdir.c b/src/dpdk22/drivers/net/i40e/i40e_fdir.c index 194f8629..f644ef3d 100644 --- a/src/dpdk22/drivers/net/i40e/i40e_fdir.c +++ b/src/dpdk22/drivers/net/i40e/i40e_fdir.c @@ -78,6 +78,7 @@ #define I40E_FDIR_FLUSH_RETRY 50 #define I40E_FDIR_FLUSH_INTERVAL_MS 5 +#define TREX_PATCH #define I40E_COUNTER_PF 2 /* Statistic counter index for one pf */ #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF) @@ -719,8 +720,10 @@ i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input, ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL; /* set len to by default */ ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN); - // TREX_PATCH +#ifdef TREX_PATCH ip->time_to_live = fdir_input->flow.ip4_flow.ttl; + ip->packet_id = rte_cpu_to_be_16(fdir_input->flow.ip4_flow.ip_id); +#endif /* * The source and destination fields in the transmitted packet * need to be presented in a reversed order with respect @@ -1145,7 +1148,11 @@ i40e_fdir_filter_programming(struct i40e_pf *pf, fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK); fdirdp->dtype_cmd_cntindex |= +#ifdef TREX_PATCH + rte_cpu_to_le_32((fdir_action->stat_count_index << +#else rte_cpu_to_le_32((pf->fdir.match_counter_index << +#endif I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & I40E_TXD_FLTR_QW1_CNTINDEX_MASK); |