blob: 942ddbd6ef3acdac00f73043b50945129ba60f1a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
/*
Ido Barnea
Cisco Systems, Inc.
*/
/*
Copyright (c) 2016-2016 Cisco Systems, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef __TREX_STATELESS_RX_CORE_H__
#define __TREX_STATELESS_RX_CORE_H__
#include <stdint.h>
#include "latency.h"
class CRxSlCfg {
public:
CRxSlCfg (){
m_max_ports = 0;
m_cps = 0.0;
}
public:
uint32_t m_max_ports;
double m_cps;// CPS
CPortLatencyHWBase * m_ports[TREX_MAX_PORTS];
};
class CRxCoreStateless {
public:
void start();
void create(const CRxSlCfg &cfg);
void reset_rx_stats(uint8_t port_id);
int get_rx_stats(uint8_t port_id, uint32_t *pkts, uint32_t *prev_pkts
, uint32_t *bytes, uint32_t *prev_bytes, int min, int max);
private:
int try_rx();
bool is_flow_stat_id(uint16_t id);
uint16_t get_hw_id(uint16_t id);
private:
uint32_t m_max_ports;
CLatencyManagerPerPort m_ports[TREX_MAX_PORTS];
};
#endif
|
