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authorDamjan Marion <damarion@cisco.com>2017-04-24 20:52:35 +0200
committerFlorin Coras <florin.coras@gmail.com>2017-04-25 00:08:57 +0000
commit6ce2232e4cd4a24f73bdfd32ae01f14cf8c1ee77 (patch)
treeae72f671334a38f1122c5f67e04bb110d7faeba1
parentb1352ed0ac39aaa7be7542275d1d43fa64ab28ac (diff)
Define cache line size for x86 32-bit
Change-Id: Ie70e805f342bda69207b9df9543f1eccb5e69612 Signed-off-by: Damjan Marion <damarion@cisco.com>
-rw-r--r--src/vppinfra/cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index 8e1f9483bde..7464b77a41b 100644
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -45,7 +45,7 @@
*/
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
-#if defined(__x86_64__) || defined(__ARM_ARCH_7A__)
+#if defined(__x86_64__) || defined(__ARM_ARCH_7A__) || defined(__i386__)
#define CLIB_LOG2_CACHE_LINE_BYTES 6
#endif