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authorZhiyong Yang <zhiyong.yang@intel.com>2018-11-05 03:45:25 -0500
committerJohn Lo <loj@cisco.com>2018-11-05 21:02:38 +0000
commitb0073e276d9e12f02f8f9874fd09ae532a0baa47 (patch)
treef2db5ddcf53e9bc48421a6ff82cbee0fcbe75f2d
parent2130284302788759c7b2644efb801b84411e342e (diff)
vxlan: prefetch extra one cacheline holding external header
For vxlan_encap, code will touch memory area before the field "data" in struct vlib_buffer_t, however so far it is not prefetched in cache yet for this graph node. After applying the patch, 2~3 cycles per pkt for vxlan4_encap can be saved on Haswell. It will bring a lot of benefits on DVN platform too. Change-Id: I26d8c57fb3d2415726be5367117d73eb715e35ad Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
-rw-r--r--src/vnet/vxlan/encap.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vnet/vxlan/encap.c b/src/vnet/vxlan/encap.c
index fdca425889e..31320900d3e 100644
--- a/src/vnet/vxlan/encap.c
+++ b/src/vnet/vxlan/encap.c
@@ -116,8 +116,8 @@ vxlan_encap_inline (vlib_main_t * vm,
vlib_prefetch_buffer_header (p2, LOAD);
vlib_prefetch_buffer_header (p3, LOAD);
- CLIB_PREFETCH (p2->data, CLIB_CACHE_LINE_BYTES, LOAD);
- CLIB_PREFETCH (p3->data, CLIB_CACHE_LINE_BYTES, LOAD);
+ CLIB_PREFETCH (p2->data - CLIB_CACHE_LINE_BYTES, 2 * CLIB_CACHE_LINE_BYTES, LOAD);
+ CLIB_PREFETCH (p3->data - CLIB_CACHE_LINE_BYTES, 2 * CLIB_CACHE_LINE_BYTES, LOAD);
}
u32 bi0 = to_next[0] = from[0];