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| author |   Damjan Marion <damarion@cisco.com> | 2023-04-17 14:11:57 +0000 |
|---|---|---|
| committer |   Florin Coras <florin.coras@gmail.com> | 2023-04-17 15:45:26 +0000 |
| commit | 687823f0178cfc672bcbaccaf27825047b18180d (patch) | |
| tree | f0a35e213f9bb20d9787237e68f85c5f7bd88b79 | |
| parent | 6a1a832346ab4b973de19e6d416703ff0fd6d1df (diff) | |
vppinfra: SFENCE requires SSE2 to be enabled
Change-Id: I0469bb91107cf0acced3cd19820db8d3712701c0
Type: fix
Fixes: eaabe07
Signed-off-by: Damjan Marion <damarion@cisco.com>
| -rw-r--r-- | src/vppinfra/clib.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vppinfra/clib.h b/src/vppinfra/clib.h index dab7eeb6f39..d14582492d6 100644 --- a/src/vppinfra/clib.h +++ b/src/vppinfra/clib.h @@ -181,7 +181,7 @@ /* Full memory barrier (read and write). */ #define CLIB_MEMORY_BARRIER() __sync_synchronize () -#if __x86_64__ +#if __SSE__ #define CLIB_MEMORY_STORE_BARRIER() __builtin_ia32_sfence () #else #define CLIB_MEMORY_STORE_BARRIER() __sync_synchronize () |