Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064)

Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto"
AKA 32, 64, or 128 bytes, or use the inferred value from the build host.

produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h

Kernels which implement the following pseudo-file (aka x86_64) are
easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size

Otherwise, extract the cpuid from /proc/cpuinfo and map it to the
cache line size.

Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74
Signed-off-by: Dave Barach <dave@barachs.net>
Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>

5 files changed, 91 insertions, 1 deletions

diff --git a/dpdk/Makefile b/dpdk/Makefile
index 331e1c34886..7b70346260c 100644
--- a/dpdk/Makefile
+++ b/dpdk/Makefile
@@ -124,6 +124,7 @@ ifneq (,$(findstring $(MIDR_PARTNUM),$(CPU_PART_CAVIUM_THUNDERX) \
 	$(CPU_PART_CAVIUM_THUNDERX_81XX) $(CPU_PART_CAVIUM_THUNDERX_83XX)))
 DPDK_TARGET           = arm64-thunderx-linuxapp-$(DPDK_CC)
 DPDK_MACHINE          = thunderx
+DPDK_CACHE_LINE_SIZE := 128
 else
 $(warning Unknown Cavium CPU)
 endif
diff --git a/src/configure.ac b/src/configure.ac
index f6ec44bb769..ad2dab1e7a3 100644
--- a/src/configure.ac
+++ b/src/configure.ac
@@ -120,6 +120,67 @@ AC_DEFUN([CC_CHECK_FLAG],
   AC_LANG_POP([C])
 ])
 
+# This function deduces the BUILD HOST cache-line size by
+# inspecting /sys and/or /proc depending on the kernel / arch in use
+as_fn_log2_cache_line_size_p()
+{
+  sysfs_cache_path="/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size"
+  m4_define([read_cache_line_size_from_sysfs], [`head -n 1 $1`])
+  m4_define([read_midr_implementer],
+            [`awk '/implementer/ {print $[]4;exit}' /proc/cpuinfo`])
+  m4_define([read_midr_cpuid],
+            [`awk '/part/ {print $[]4;exit}' /proc/cpuinfo`])
+
+  #Check if sysfs path exists,to ignore warning, else do manual mapping
+  AC_CHECK_FILE($sysfs_cache_path,
+    [
+      cache_line_size=read_cache_line_size_from_sysfs($sysfs_cache_path);
+      if test $cache_line_size = "32"  ; then
+          log2_cache_line_size="5";
+      elif test $cache_line_size = "64"  ; then
+          log2_cache_line_size="6";
+      elif test $cache_line_size = "128"  ; then
+          log2_cache_line_size="7";
+      fi
+      AC_MSG_NOTICE([cache_line_size/log2_cache_line_size deduced as $cache_line_size/$log2_cache_line_size])
+    ],
+    [
+        #Define Implementer Ids here
+        implementer_id_cavium=0x43
+
+        #Define CPU Ids here
+        cpu_id_cavium_thunderx_cn88xx=0x0a1
+        cpu_id_cavium_thunderx2_cn99xx=0x0af
+
+        implementer=read_midr_implementer()
+        cpuid=read_midr_cpuid()
+
+        AC_MSG_CHECKING([for implementerid/cpuid to set log2_cache_line_size])
+
+        # Switch case to map log2_cache_line_size for implementer/cpuid combination.
+        # Default case of Switch sets log2_cache_line_size to 6
+        AS_CASE($implementer,
+              #Switch Case for Cavium SoC's
+              [$implementer_id_cavium],
+                  [AS_CASE($cpuid,
+                      #Only ThunderX2 is 64B. Remaining chips are 128B
+                      [$cpu_id_cavium_thunderx2_cn99xx],
+                            [AC_MSG_RESULT([Cavium/ThunderX2]);log2_cache_line_size=6],
+                      [$cpu_id_cavium_thunderx_cn88xx],
+                            [AC_MSG_RESULT([Cavium/ThunderX]);log2_cache_line_size=7],
+                      [log2_cache_line_size=7;AC_MSG_RESULT([Cavium/OCTEONTx($cpuid)])]
+                   )],
+              #Add implementer specific case here:
+
+              #Default case: 64B for all SoC's
+              [log2_cache_line_size=6;AC_MSG_RESULT([$implementer/$cpuid])]
+        )
+      AC_MSG_NOTICE([log2_cache_line_size deduced as $log2_cache_line_size])
+    ]
+  )
+  echo $log2_cache_line_size
+}
+
 ###############################################################################
 # configure arguments
 ###############################################################################
@@ -144,6 +205,15 @@ WITHOUT_ARG(apicli,	[Disable binary api CLI])
 WITHOUT_ARG(mbedtls,	[Disable mbedtls])
 WITHOUT_ARG(libnuma,	[for non numa architectures])
 
+AC_ARG_WITH(log2-cache-line-bytes,
+            AC_HELP_STRING([--with-log2-cache-line-bytes],[Set the cache line size, --with-log2-cache-line-bytes=5|6|7|auto]),
+	    [case $with_log2_cache_line_bytes in
+	      5 | 6 | 7);;
+	      auto) with_log2_cache_line_bytes=`as_fn_log2_cache_line_size_p`;;
+              *) with_log2_cache_line_bytes="CONFIG_ERROR";;
+	      esac],
+              [with_log2_cache_line_bytes=`as_fn_log2_cache_line_size_p`])
+
 AC_ARG_WITH(unix,
             AC_HELP_STRING([--with-unix],[Compile unix version of clib]),
 	    [],
@@ -206,6 +276,7 @@ AS_IF([test "$cc_flag_check" = yes],
 ###############################################################################
 
 AC_SUBST(PRE_DATA_SIZE,		[$with_pre_data])
+AC_SUBST(LOG2_CACHE_LINE_BYTES, [$with_log2_cache_line_bytes])
 AC_SUBST(APICLI,		[-DVPP_API_TEST_BUILTIN=${n_with_apicli}])
 
 AC_DEFINE_UNQUOTED(DPDK_SHARED_LIB,	[${n_enable_dpdk_shared}])
@@ -367,6 +438,7 @@ PRINT_VAL([includedir], ${includedir})
 PRINT_VAL([CFLAGS], ${CFLAGS})
 PRINT_VAL([CPPFLAGS], ${CPPFLAGS})
 PRINT_VAL([LDFLAGS], ${LDFLAGS})
+PRINT_VAL([LOG2_CACHE_LINE_BYTES], ${with_log2_cache_line_bytes})
 AM_COND_IF([ENABLE_JAPI],
 [
   PRINT_VAL([JAVA_VERSION], ${JAVA_VERSION})
diff --git a/src/plugins/dpdk/device/init.c b/src/plugins/dpdk/device/init.c
index b5a8e3bcd4b..ceaa5bb61e9 100644
--- a/src/plugins/dpdk/device/init.c
+++ b/src/plugins/dpdk/device/init.c
@@ -1691,6 +1691,8 @@ dpdk_init (vlib_main_t * vm)
 		 "Data in cache line 0 is bigger than cache line size");
   STATIC_ASSERT (offsetof (frame_queue_trace_t, cacheline0) == 0,
 		 "Cache line marker must be 1st element in frame_queue_trace_t");
+  STATIC_ASSERT (RTE_CACHE_LINE_SIZE == 1 << CLIB_LOG2_CACHE_LINE_BYTES,
+		 "DPDK RTE CACHE LINE SIZE does not match with 1<<CLIB_LOG2_CACHE_LINE_BYTES");
 
   dm->vlib_main = vm;
   dm->vnet_main = vnet_get_main ();
diff --git a/src/vppinfra.am b/src/vppinfra.am
index ec271e6dc63..d138a26d8cf 100644
--- a/src/vppinfra.am
+++ b/src/vppinfra.am
@@ -13,6 +13,17 @@
 
 lib_LTLIBRARIES += libvppinfra.la
 
+BUILT_SOURCES += vppinfra/config.h
+
+vppinfra/config.h:
+	@echo "/** Autogenerated by Autotools **/" > $@
+	@echo "#ifndef included_clib_config_h" >> $@
+	@echo "#define included_clib_config_h" >> $@
+	@echo "#ifndef CLIB_LOG2_CACHE_LINE_BYTES " >> $@
+	@echo "#define CLIB_LOG2_CACHE_LINE_BYTES " @LOG2_CACHE_LINE_BYTES@ >> $@
+	@echo "#endif " >> $@
+	@echo "#endif " >> $@
+
 TESTS = 
 
 if ENABLE_TESTS
@@ -197,6 +208,7 @@ nobase_include_HEADERS = \
   vppinfra/bitops.h \
   vppinfra/byte_order.h \
   vppinfra/cache.h \
+  vppinfra/config.h \
   vppinfra/clib.h \
   vppinfra/clib_error.h \
   vppinfra/cpu.h \
diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index e5c678eb517..ac0835523cb 100644
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -41,10 +41,13 @@
 #include <vppinfra/error_bootstrap.h>
 
 /*
- * Allow CFLAGS to override the arch-specific cache line size
+ * Allow CFLAGS to override the configured / deduced cache line size
  */
 #ifndef CLIB_LOG2_CACHE_LINE_BYTES
 
+/* defines CLIB_LOG2_CACHE_LINE_BYTES */
+#include <vppinfra/config.h>
+
 /* Default cache line size of 64 bytes. */
 #ifndef CLIB_LOG2_CACHE_LINE_BYTES
 #define CLIB_LOG2_CACHE_LINE_BYTES 6