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| author |   Tianyu Li <tianyu.li@arm.com> | 2021-06-23 07:35:03 +0000 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2021-07-02 14:28:24 +0000 |
| commit | 70b1cbdf2bd7687f840a59475ca769c9bab907c9 (patch) | |
| tree | 911e87072e23cb58243293f126281b8613a50896 /build-root | |
| parent | ecadf6a5395968092e093f7fa1d40a17762ebac1 (diff) | |
vlib: fix buffer pool alignment size
Alignment size should be CLIB_CACHE_LINE_BYTES(64)
instead of CLIB_LOG2_CACHE_LINE_BYTES(6)
Type: fix
Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Change-Id: If2d5ae324093be64454377866297f5e76ccddc93
Diffstat (limited to 'build-root')
0 files changed, 0 insertions, 0 deletions