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authorPaul Vinciguerra <pvinci@vinciconsulting.com>2019-10-27 17:28:10 -0400
committerDave Barach <openvpp@barachs.net>2019-10-28 13:51:13 +0000
commit7fa3dd2881be537ec6144850064ad1419dc12f3e (patch)
tree7fa013d6e23f16f73b0ca97628c1374a009b49bd /docs/overview/performance
parent3b5e222f8a4d0ccd4ec4eace2551491f13de85d9 (diff)
docs: cleanup typos on readthrough
Type: style Change-Id: I3b15035ea6c13cd1ca3cdc9dfa9b10a6e1be9880 Signed-off-by: Paul Vinciguerra <pvinci@vinciconsulting.com>
Diffstat (limited to 'docs/overview/performance')
-rw-r--r--docs/overview/performance/index.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/overview/performance/index.rst b/docs/overview/performance/index.rst
index 1c250206fcf..25e3897ff37 100644
--- a/docs/overview/performance/index.rst
+++ b/docs/overview/performance/index.rst
@@ -27,7 +27,7 @@ These features have been designed to take full advantage of common micro-process
* Reducing cache and TLS misses by processing packets in vectors
* Realizing `IPC <https://en.wikipedia.org/wiki/Instructions_per_cycle>`_ gains with vector instructions such as: SSE, AVX and NEON
* Eliminating mode switching, context switches and blocking, to always be doing useful work
-* Cache-lined aliged buffers for cache and memory efficiency
+* Cache-lined aligned buffers for cache and memory efficiency
Packet Throughput Graphs