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authorDamjan Marion <damarion@cisco.com>2016-11-24 22:20:05 +0100
committerNeale Ranns <nranns@cisco.com>2016-11-25 09:27:31 +0000
commit30230dd7f854e77008b257c8be1de648e473338e (patch)
tree53e99fc7b066593ae9672cfbb80511362c53b450 /doxygen
parent23a7412bda2c14b21deda66bc5555c9ee680dec8 (diff)
l2: fix latency issue casued by unnecesary read of previous cacheline
In majority of cases ethernet header sits at the beggining of cacheline. Reading (dst_mac - 2) into 64 bit register is much more expensive than doing simple bitwise shift, specially if previous cacheline is not prefetched. Change-Id: I35e53eae735098fb917a87c307e60a87e76e460f Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'doxygen')
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