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authorZhiyong Yang <zhiyong.yang@intel.com>2020-05-15 22:32:34 +0800
committerDamjan Marion <dmarion@me.com>2020-06-27 10:26:13 +0000
commit975a3cbb130fe7f3d5415dee7c05ea5e7bc59daf (patch)
tree7e4cc9763ac70b365a4ca2665d254b024dba04e1 /extras/deprecated/vppinfra/test_phash.c
parentd352bf8276f33f33e4af5e8a7b85dad8187f531d (diff)
l2: performance enhancement in l2input
Short Load/Stores combined with prefetching in the beginning of the loop place too much pressure on AGUs and memory accesses. The patch interleaves load/store operations with computational operations to alleviate the pain point. vlib_get_buffers is also leveraged. Redefine u8 dst_and_src[12] instead of dst[6] and src[6] in struct l2input_trace_t in order to merge two copys into one. Type: improvement Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com> Change-Id: I7d3df7732c476069235e3019c68f0f53bca9637e
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