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authorMarco Varlese <marco.varlese@suse.com>2018-09-07 11:02:26 +0200
committerDamjan Marion <dmarion@me.com>2018-09-07 19:36:48 +0000
commit0745036cb9ead1a3aaf9686c8c8046cb7285ea52 (patch)
treedd63943e0dd287bf6588166d0cac8277994f1e89 /extras/scripts/pci-nic-bind-to-kernel
parent4e588aa7ca89b966fd9ec2fc6b02d75df23ae648 (diff)
Cavium OcteonTX: cache line fix
According to Nitin Saxena ThunderX2 machine has 64B cache line whilst all others are 128B. According to Damjan, Nitin's previous patch broke compilation for all non-Cavium machines. This patch should make everything happy again. Change-Id: I8c5c2661f9f2f9c3e9b0965a277712f9a1eefa5f Signed-off-by: Marco Varlese <marco.varlese@suse.com>
Diffstat (limited to 'extras/scripts/pci-nic-bind-to-kernel')
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