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| author |   Junfeng Wang <Drenfong.Wang@intel.com> | 2021-03-09 16:44:57 +0800 |
|---|---|---|
| committer |   John Lo <lojultra2020@outlook.com> | 2021-03-19 21:34:16 +0000 |
| commit | 290526e3c72888ac05928ed0a6dddee02f7df650 (patch) | |
| tree | 5117191488c7107d6404abaaca97d76022e7e759 /src/plugins/geneve/geneve.h | |
| parent | 162b70d50aaf5daa744417818c01cae573580f6f (diff) | |
vxlan: add tunnel cache to graph node
Type: improvement
Signed-off-by: Drenfong Wong <drenfong.wang@intel.com>
Change-Id: Ia81aaa86fe071cbbed028cc85c5f3fa0f1940a0f
Diffstat (limited to 'src/plugins/geneve/geneve.h')
| -rw-r--r-- | src/plugins/geneve/geneve.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/plugins/geneve/geneve.h b/src/plugins/geneve/geneve.h index d41a49a7ff6..0cc14214b9b 100644 --- a/src/plugins/geneve/geneve.h +++ b/src/plugins/geneve/geneve.h @@ -186,6 +186,11 @@ typedef struct vnet_main_t *vnet_main; u16 msg_id_base; + /* cache for last 8 geneve tunnel */ +#ifdef CLIB_HAVE_VEC512 + vtep4_cache_t vtep4_u512; +#endif + } geneve_main_t; extern geneve_main_t geneve_main; |