summaryrefslogtreecommitdiffstats
path: root/src/plugins/perfmon/arm/bundle/cache_data_tlb.c
diff options
context:
space:
mode:
authorZachary Leaf <zachary.leaf@arm.com>2022-05-23 06:23:40 -0500
committerDamjan Marion <dmarion@0xa5.net>2022-07-12 15:29:23 +0000
commitaf82211d33c9e68c95097f74f04169ec40bd960c (patch)
tree9a93765d5fd583de43bb27557d0ac52358e09469 /src/plugins/perfmon/arm/bundle/cache_data_tlb.c
parent268d7be66b8b48a230e06de645e3a8b7de29d93c (diff)
perfmon: add Arm event bundles
Included statistic bundles (all NODE type): - Instructions and CPU cycles, including IPC - Data cache access/refills/% - Data TLB cache access/refills/% - Instruction cache access/refills/% - Instruction TLB cache access/refills/% - Memory/Bus accesses, memory errors - Branch (mis)predictions, architecturally & speculatively executed - Processor frontend/backend stalls (stalled cycles) Type: feature Signed-off-by: Zachary Leaf <zachary.leaf@arm.com> Tested-by: Jieqiang Wang <jieqiang.wang@arm.com> Change-Id: I7ea4a27c8df8fc7222b743a98bdceaff727e4112
Diffstat (limited to 'src/plugins/perfmon/arm/bundle/cache_data_tlb.c')
-rw-r--r--src/plugins/perfmon/arm/bundle/cache_data_tlb.c106
1 files changed, 106 insertions, 0 deletions
diff --git a/src/plugins/perfmon/arm/bundle/cache_data_tlb.c b/src/plugins/perfmon/arm/bundle/cache_data_tlb.c
new file mode 100644
index 00000000000..9adb2bc18b2
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/cache_data_tlb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+ L1D_TLB,
+ L1D_TLB_REFILL,
+ L2D_TLB,
+ L2D_TLB_REFILL
+};
+
+static u8 *
+format_arm_cache_data_tlb (u8 *s, va_list *args)
+{
+ perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+ int row = va_arg (*args, int);
+
+ switch (row)
+ {
+ case 0:
+ s = format (s, "%.2f", (f64) ns->value[L1D_TLB] / ns->n_packets);
+ break;
+
+ case 1:
+ s = format (s, "%.2f", (f64) ns->value[L1D_TLB_REFILL] / ns->n_packets);
+ break;
+
+ case 2:
+ s = format (s, "%.2f%%",
+ (ns->value[L1D_TLB] ? (f64) ns->value[L1D_TLB_REFILL] /
+ ns->value[L1D_TLB] * 100 :
+ 0));
+ break;
+
+ case 3:
+ s = format (s, "%.2f", (f64) ns->value[L2D_TLB] / ns->n_packets);
+ break;
+
+ case 4:
+ s = format (s, "%.2f", (f64) ns->value[L2D_TLB_REFILL] / ns->n_packets);
+ break;
+
+ case 5:
+ s = format (s, "%.2f%%",
+ (ns->value[L2D_TLB] ? (f64) ns->value[L2D_TLB_REFILL] /
+ ns->value[L2D_TLB] * 100 :
+ 0));
+ break;
+
+ case 6:
+ s = format (s, "%llu", ns->n_packets);
+ break;
+ }
+ return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_cache_data_tlb) = {
+ .name = "cache-data-tlb",
+ .description = "L1/L2 data TLB cache accesses, refills, walks per packet",
+ .source = "arm",
+ .type = PERFMON_BUNDLE_TYPE_NODE,
+ .events[0] = ARMV8_PMUV3_L1D_TLB,
+ .events[1] = ARMV8_PMUV3_L1D_TLB_REFILL,
+ .events[2] = ARMV8_PMUV3_L2D_TLB,
+ .events[3] = ARMV8_PMUV3_L2D_TLB_REFILL,
+ .n_events = 4,
+ .n_columns = 7,
+ .format_fn = format_arm_cache_data_tlb,
+ .column_headers = PERFMON_STRINGS ("L1D-TLB: access", "refill", "\%*",
+ "L2D-TLB: access", "refill", "\%*",
+ "pkts"),
+ /*
+ * set a bit for every event used in each column
+ * this allows us to disable columns at bundle registration if an
+ * event is not supported
+ */
+ .column_events = PERFMON_COLUMN_EVENTS (
+ SET_BIT (L1D_TLB), SET_BIT (L1D_TLB_REFILL),
+ SET_BIT (L1D_TLB) | SET_BIT (L1D_TLB_REFILL), SET_BIT (L2D_TLB),
+ SET_BIT (L2D_TLB_REFILL), SET_BIT (L2D_TLB) | SET_BIT (L2D_TLB_REFILL), 0),
+ .footer =
+ "all stats are per packet except refill rates (\%)\n"
+ "*\% percentage shown is total refills/accesses\n\n"
+ "TLB: Memory-read operation or Memory-write operation that"
+ " causes a TLB access to at least the Level 1/2 data or unified TLB.\n"
+ "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+ " event numbers for full description.\n"
+};