perfmon: add Arm event bundles

Included statistic bundles (all NODE type):
  - Instructions and CPU cycles, including IPC
  - Data cache access/refills/%
  - Data TLB cache access/refills/%
  - Instruction cache access/refills/%
  - Instruction TLB cache access/refills/%
  - Memory/Bus accesses, memory errors
  - Branch (mis)predictions, architecturally & speculatively executed
  - Processor frontend/backend stalls (stalled cycles)

Type: feature
Signed-off-by: Zachary Leaf <zachary.leaf@arm.com>
Tested-by: Jieqiang Wang <jieqiang.wang@arm.com>
Change-Id: I7ea4a27c8df8fc7222b743a98bdceaff727e4112

8 files changed, 866 insertions, 0 deletions

diff --git a/src/plugins/perfmon/arm/bundle/branch_pred.c b/src/plugins/perfmon/arm/bundle/branch_pred.c
new file mode 100644
index 00000000000..7ab656f2758
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/branch_pred.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  BR_RETIRED,
+  BR_MIS_PRED_RETIRED,
+  BR_PRED,
+  BR_MIS_PRED
+};
+
+static u8 *
+format_arm_branch_pred (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%.2f", (f64) ns->value[BR_RETIRED] / ns->n_calls);
+      break;
+
+    case 1:
+      s = format (s, "%.2f", (f64) ns->value[BR_RETIRED] / ns->n_packets);
+      break;
+
+    case 2:
+      s =
+	format (s, "%.2f", (f64) ns->value[BR_MIS_PRED_RETIRED] / ns->n_calls);
+      break;
+
+    case 3:
+      s = format (s, "%.2f",
+		  (f64) ns->value[BR_MIS_PRED_RETIRED] / ns->n_packets);
+      break;
+
+    case 4:
+      s =
+	format (s, "%.2f%%",
+		(ns->value[BR_RETIRED] ? (f64) ns->value[BR_MIS_PRED_RETIRED] /
+					   ns->value[BR_RETIRED] * 100 :
+					       0));
+      break;
+
+    case 5:
+      s = format (s, "%.2f", (f64) ns->value[BR_PRED] / ns->n_calls);
+      break;
+
+    case 6:
+      s = format (s, "%.2f", (f64) ns->value[BR_PRED] / ns->n_packets);
+      break;
+
+    case 7:
+      s = format (s, "%.2f", (f64) ns->value[BR_MIS_PRED] / ns->n_calls);
+      break;
+
+    case 8:
+      s = format (s, "%.2f", (f64) ns->value[BR_MIS_PRED] / ns->n_packets);
+      break;
+
+    case 9:
+      s = format (s, "%.2f%%",
+		  (ns->value[BR_PRED] ?
+			   (f64) ns->value[BR_MIS_PRED] / ns->value[BR_PRED] * 100 :
+			   0));
+      break;
+
+    case 10:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_branch_pred) = {
+  .name = "branch-pred",
+  .description = "Branch (mis)predictions per call/packet",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_BR_RETIRED,
+  .events[1] = ARMV8_PMUV3_BR_MIS_PRED_RETIRED,
+  .events[2] = ARMV8_PMUV3_BR_PRED,
+  .events[3] = ARMV8_PMUV3_BR_MIS_PRED,
+  .n_events = 4,
+  .n_columns = 11,
+  .format_fn = format_arm_branch_pred,
+  .column_headers = PERFMON_STRINGS ("[1.1]", "[1.2]", "[1.3]", "[1.4]", "\%",
+				     "[2.1]", "[2.2]", "[2.3]", "[2.4]", "\%",
+				     "pkts"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (
+    SET_BIT (BR_RETIRED), SET_BIT (BR_RETIRED), SET_BIT (BR_MIS_PRED_RETIRED),
+    SET_BIT (BR_MIS_PRED_RETIRED),
+    SET_BIT (BR_RETIRED) | SET_BIT (BR_MIS_PRED_RETIRED), SET_BIT (BR_PRED),
+    SET_BIT (BR_PRED), SET_BIT (BR_MIS_PRED), SET_BIT (BR_MIS_PRED),
+    SET_BIT (BR_PRED) | SET_BIT (BR_MIS_PRED), 0),
+  .footer =
+    "An instruction that has been executed and retired is defined to\n"
+    "be architecturally executed. When a PE can perform speculative\n"
+    "execution, an instruction is not architecturally executed if the\n"
+    "PE discards the results of the speculative execution.\n\n"
+    "Per node statistics:\n"
+    "[1] Branch instruction architecturally executed\n"
+    "    [1.1] Branches/call\n"
+    "    [1.2] Branches/pkt\n"
+    "    [1.3] Mispredicted/call \n"
+    "    [1.4] Mispredicted/pkt\n"
+    "    [\%] Percentage of branches mispredicted\n"
+    "[2] Predictable branch speculatively executed\n"
+    "    [2.1] Branches/call\n"
+    "    [2.2] Branches/pkt\n"
+    "    [2.3] Mispredicted/call \n"
+    "    [2.4] Mispredicted/pkt\n"
+    "    [\%] Percentage of branches mispredicted\n\n"
+    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+    " event numbers for full description.\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/cache_data.c b/src/plugins/perfmon/arm/bundle/cache_data.c
new file mode 100644
index 00000000000..d7587700a8c
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/cache_data.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  L1D_CACHE,
+  L1D_CACHE_REFILL,
+  L2D_CACHE,
+  L2D_CACHE_REFILL,
+  L3D_CACHE,
+  L3D_CACHE_REFILL
+};
+
+static u8 *
+format_arm_cache_data (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%.2f", (f64) ns->value[L1D_CACHE] / ns->n_packets);
+      break;
+
+    case 1:
+      s =
+	format (s, "%.2f", (f64) ns->value[L1D_CACHE_REFILL] / ns->n_packets);
+      break;
+
+    case 2:
+      s = format (s, "%.2f%%",
+		  (ns->value[L1D_CACHE] ? (f64) ns->value[L1D_CACHE_REFILL] /
+					    ns->value[L1D_CACHE] * 100 :
+						0));
+      break;
+
+    case 3:
+      s = format (s, "%.2f", (f64) ns->value[L2D_CACHE] / ns->n_packets);
+      break;
+
+    case 4:
+      s =
+	format (s, "%.2f", (f64) ns->value[L2D_CACHE_REFILL] / ns->n_packets);
+      break;
+
+    case 5:
+      s = format (s, "%.2f%%",
+		  (ns->value[L2D_CACHE] ? (f64) ns->value[L2D_CACHE_REFILL] /
+					    ns->value[L2D_CACHE] * 100 :
+						0));
+      break;
+
+    case 6:
+      s = format (s, "%.2f", (f64) ns->value[L3D_CACHE] / ns->n_packets);
+      break;
+
+    case 7:
+      s =
+	format (s, "%.2f", (f64) ns->value[L3D_CACHE_REFILL] / ns->n_packets);
+      break;
+
+    case 8:
+      s = format (s, "%.2f%%",
+		  (ns->value[L3D_CACHE] ? (f64) ns->value[L3D_CACHE_REFILL] /
+					    ns->value[L3D_CACHE] * 100 :
+						0));
+      break;
+
+    case 9:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_cache_data) = {
+  .name = "cache-data",
+  .description = "L1D/L2D/L3D data cache accesses and refills per packet",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_L1D_CACHE,
+  .events[1] = ARMV8_PMUV3_L1D_CACHE_REFILL,
+  .events[2] = ARMV8_PMUV3_L2D_CACHE,
+  .events[3] = ARMV8_PMUV3_L2D_CACHE_REFILL,
+  .events[4] = ARMV8_PMUV3_L3D_CACHE,
+  .events[5] = ARMV8_PMUV3_L3D_CACHE_REFILL,
+  .n_events = 6,
+  .n_columns = 10,
+  .format_fn = format_arm_cache_data,
+  .column_headers = PERFMON_STRINGS ("L1D: access", "refill", "\%*",
+				     "L2D: access", "refill", "\%*",
+				     "L3D: access", "refill", "\%*", "pkts"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (
+    SET_BIT (L1D_CACHE), SET_BIT (L1D_CACHE_REFILL),
+    SET_BIT (L1D_CACHE) | SET_BIT (L1D_CACHE_REFILL), SET_BIT (L2D_CACHE),
+    SET_BIT (L2D_CACHE_REFILL),
+    SET_BIT (L2D_CACHE) | SET_BIT (L2D_CACHE_REFILL), SET_BIT (L3D_CACHE),
+    SET_BIT (L3D_CACHE_REFILL),
+    SET_BIT (L3D_CACHE) | SET_BIT (L3D_CACHE_REFILL), 0),
+  .footer = "all stats are per packet except refill rate (\%)\n"
+	    "*\% percentage shown is total refills/accesses\n\n"
+	    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+	    " event numbers for full description.\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/cache_data_tlb.c b/src/plugins/perfmon/arm/bundle/cache_data_tlb.c
new file mode 100644
index 00000000000..9adb2bc18b2
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/cache_data_tlb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  L1D_TLB,
+  L1D_TLB_REFILL,
+  L2D_TLB,
+  L2D_TLB_REFILL
+};
+
+static u8 *
+format_arm_cache_data_tlb (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%.2f", (f64) ns->value[L1D_TLB] / ns->n_packets);
+      break;
+
+    case 1:
+      s = format (s, "%.2f", (f64) ns->value[L1D_TLB_REFILL] / ns->n_packets);
+      break;
+
+    case 2:
+      s = format (s, "%.2f%%",
+		  (ns->value[L1D_TLB] ? (f64) ns->value[L1D_TLB_REFILL] /
+					  ns->value[L1D_TLB] * 100 :
+					      0));
+      break;
+
+    case 3:
+      s = format (s, "%.2f", (f64) ns->value[L2D_TLB] / ns->n_packets);
+      break;
+
+    case 4:
+      s = format (s, "%.2f", (f64) ns->value[L2D_TLB_REFILL] / ns->n_packets);
+      break;
+
+    case 5:
+      s = format (s, "%.2f%%",
+		  (ns->value[L2D_TLB] ? (f64) ns->value[L2D_TLB_REFILL] /
+					  ns->value[L2D_TLB] * 100 :
+					      0));
+      break;
+
+    case 6:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_cache_data_tlb) = {
+  .name = "cache-data-tlb",
+  .description = "L1/L2 data TLB cache accesses, refills, walks per packet",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_L1D_TLB,
+  .events[1] = ARMV8_PMUV3_L1D_TLB_REFILL,
+  .events[2] = ARMV8_PMUV3_L2D_TLB,
+  .events[3] = ARMV8_PMUV3_L2D_TLB_REFILL,
+  .n_events = 4,
+  .n_columns = 7,
+  .format_fn = format_arm_cache_data_tlb,
+  .column_headers = PERFMON_STRINGS ("L1D-TLB: access", "refill", "\%*",
+				     "L2D-TLB: access", "refill", "\%*",
+				     "pkts"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (
+    SET_BIT (L1D_TLB), SET_BIT (L1D_TLB_REFILL),
+    SET_BIT (L1D_TLB) | SET_BIT (L1D_TLB_REFILL), SET_BIT (L2D_TLB),
+    SET_BIT (L2D_TLB_REFILL), SET_BIT (L2D_TLB) | SET_BIT (L2D_TLB_REFILL), 0),
+  .footer =
+    "all stats are per packet except refill rates (\%)\n"
+    "*\% percentage shown is total refills/accesses\n\n"
+    "TLB: Memory-read operation or Memory-write operation that"
+    " causes a TLB access to at least the Level 1/2 data or unified TLB.\n"
+    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+    " event numbers for full description.\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/cache_inst.c b/src/plugins/perfmon/arm/bundle/cache_inst.c
new file mode 100644
index 00000000000..b9d49c09e12
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/cache_inst.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  L1I_CACHE,
+  L1I_CACHE_REFILL,
+  L2I_CACHE,
+  L2I_CACHE_REFILL
+};
+
+static u8 *
+format_arm_cache_inst (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%.2f", (f64) ns->value[L1I_CACHE] / ns->n_packets);
+      break;
+
+    case 1:
+      s =
+	format (s, "%.2f", (f64) ns->value[L1I_CACHE_REFILL] / ns->n_packets);
+      break;
+
+    case 2:
+      s = format (s, "%.2f%%",
+		  (ns->value[L1I_CACHE] ? (f64) ns->value[L1I_CACHE_REFILL] /
+					    ns->value[L1I_CACHE] * 100 :
+						0));
+      break;
+
+    case 3:
+      s = format (s, "%.2f", (f64) ns->value[L2I_CACHE] / ns->n_packets);
+      break;
+
+    case 4:
+      s =
+	format (s, "%.2f", (f64) ns->value[L2I_CACHE_REFILL] / ns->n_packets);
+      break;
+
+    case 5:
+      s = format (s, "%.2f%%",
+		  (ns->value[L2I_CACHE] ? (f64) ns->value[L2I_CACHE_REFILL] /
+					    ns->value[L2I_CACHE] * 100 :
+						0));
+      break;
+
+    case 6:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_cache_inst) = {
+  .name = "cache-inst",
+  .description = "L1I/L2I instruction cache accesses and refills per packet",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_L1I_CACHE,
+  .events[1] = ARMV8_PMUV3_L1I_CACHE_REFILL,
+  .events[2] = ARMV8_PMUV3_L2I_CACHE,
+  .events[3] = ARMV8_PMUV3_L2I_CACHE_REFILL,
+  .n_events = 4,
+  .n_columns = 7,
+  .format_fn = format_arm_cache_inst,
+  .column_headers = PERFMON_STRINGS ("L1I: access", "refill", "\%*",
+				     "L2I: access", "refill", "\%*", "pkts"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (
+    SET_BIT (L1I_CACHE), SET_BIT (L1I_CACHE_REFILL),
+    SET_BIT (L1I_CACHE) | SET_BIT (L1I_CACHE_REFILL), SET_BIT (L2I_CACHE),
+    SET_BIT (L2I_CACHE_REFILL),
+    SET_BIT (L2I_CACHE) | SET_BIT (L2I_CACHE_REFILL), 0),
+  .footer = "all stats are per packet except refill rate (\%)\n"
+	    "*\% percentage shown is total refills/accesses\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/cache_inst_tlb.c b/src/plugins/perfmon/arm/bundle/cache_inst_tlb.c
new file mode 100644
index 00000000000..7366be2fc16
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/cache_inst_tlb.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+enum /* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+{
+  L1I_TLB,
+  L1I_TLB_REFILL,
+  L2I_TLB,
+  L2I_TLB_REFILL,
+};
+
+static u8 *
+format_arm_cache_inst_tlb (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%.2f", (f64) ns->value[L1I_TLB] / ns->n_packets);
+      break;
+
+    case 1:
+      s = format (s, "%.2f", (f64) ns->value[L1I_TLB_REFILL] / ns->n_packets);
+      break;
+
+    case 2:
+      s = format (s, "%.2f%%",
+		  (ns->value[L1I_TLB] ? (f64) ns->value[L1I_TLB_REFILL] /
+					  ns->value[L1I_TLB] * 100 :
+					      0));
+      break;
+
+    case 3:
+      s = format (s, "%.2f", (f64) ns->value[L2I_TLB] / ns->n_packets);
+      break;
+
+    case 4:
+      s = format (s, "%.2f", (f64) ns->value[L2I_TLB_REFILL] / ns->n_packets);
+      break;
+
+    case 5:
+      s = format (s, "%.2f%%",
+		  (ns->value[L2I_TLB] ? (f64) ns->value[L2I_TLB_REFILL] /
+					  ns->value[L2I_TLB] * 100 :
+					      0));
+      break;
+
+    case 6:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_cache_inst_tlb) = {
+  .name = "cache-inst-tlb",
+  .description =
+    "L1/L2 instruction TLB cache accesses, refills, walks per packet",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_L1I_TLB,
+  .events[1] = ARMV8_PMUV3_L1I_TLB_REFILL,
+  .events[2] = ARMV8_PMUV3_L2I_TLB,
+  .events[3] = ARMV8_PMUV3_L2I_TLB_REFILL,
+  .n_events = 4,
+  .n_columns = 7,
+  .format_fn = format_arm_cache_inst_tlb,
+  .column_headers = PERFMON_STRINGS ("L1I-TLB: access", "refill", "\%*",
+				     "L2I-TLB: access", "refill", "\%*",
+				     "pkts"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (
+    SET_BIT (L1I_TLB), SET_BIT (L1I_TLB_REFILL),
+    SET_BIT (L1I_TLB) | SET_BIT (L1I_TLB_REFILL), SET_BIT (L2I_TLB),
+    SET_BIT (L2I_TLB_REFILL), SET_BIT (L2I_TLB) | SET_BIT (L2I_TLB_REFILL), 0),
+  .footer = "all stats are per packet except refill rate (\%)\n"
+	    "*\% percentage shown is total refills/accesses\n\n"
+	    "TLB: Instruction memory access that causes a TLB access to at "
+	    "least the Level 1/2 instruction TLB.\n"
+	    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+	    " event numbers for full description.\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/inst_clock.c b/src/plugins/perfmon/arm/bundle/inst_clock.c
new file mode 100644
index 00000000000..272e524cffc
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/inst_clock.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  CPU_CYCLES,
+  INST_RETIRED
+};
+
+static u8 *
+format_arm_inst_clock (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+
+    case 1:
+      s = format (s, "%llu", ns->n_calls);
+      break;
+
+    case 2:
+      s = format (s, "%llu", ns->value[0]); /* Cycles */
+      break;
+
+    case 3:
+      s = format (s, "%llu", ns->value[1]); /* Inst */
+      break;
+
+    case 4:
+      s = format (s, "%.2f",
+		  (f64) ns->n_packets / ns->n_calls); /* Packets/Call */
+      break;
+
+    case 5:
+      s = format (s, "%.2f",
+		  (f64) ns->value[0] / ns->n_packets); /* Clocks/Packet */
+      break;
+
+    case 6:
+      s =
+	format (s, "%.2f",
+		(f64) ns->value[1] / ns->n_packets); /* Instructions/Packet */
+      break;
+
+    case 7:
+      s = format (s, "%.2f", (f64) ns->value[1] / ns->value[0]); /* IPC */
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_inst_clock) = {
+  .name = "inst-and-clock",
+  .description =
+    "CPU cycles, instructions, instructions/packet, cycles/packet and IPC",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_CPU_CYCLES,
+  .events[1] = ARMV8_PMUV3_INST_RETIRED,
+  .n_events = 2,
+  .n_columns = 8,
+  .format_fn = format_arm_inst_clock,
+  .column_headers = PERFMON_STRINGS ("Packets", "Calls", "CPU Cycles", "Inst*",
+				     "Pkts/Call", "Cycles/Pkt", "Inst/Pkt",
+				     "IPC"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events =
+    PERFMON_COLUMN_EVENTS (0, 0, SET_BIT (CPU_CYCLES), SET_BIT (INST_RETIRED),
+			   0, SET_BIT (CPU_CYCLES), SET_BIT (INST_RETIRED),
+			   SET_BIT (CPU_CYCLES) | SET_BIT (INST_RETIRED)),
+  .footer = "* Instructions retired: the counter increments for every "
+	    "architecturally executed instruction\n"
+	    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+	    " event numbers for full description.\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/mem_access.c b/src/plugins/perfmon/arm/bundle/mem_access.c
new file mode 100644
index 00000000000..cfe8f4dc425
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/mem_access.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  MEM_ACCESS,
+  BUS_ACCESS,
+  MEMORY_ERROR
+};
+
+static u8 *
+format_arm_memory_access (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%.2f", (f64) ns->value[MEM_ACCESS] / ns->n_packets);
+      break;
+
+    case 1:
+      s = format (s, "%.3f", (f64) ns->value[BUS_ACCESS] / ns->n_packets);
+      break;
+
+    case 2:
+      s = format (s, "%llu", ns->value[MEMORY_ERROR]);
+      break;
+
+    case 3:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_memory_access) = {
+  .name = "memory-access",
+  .description = "Memory/bus accesses per pkt + total memory errors",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_MEM_ACCESS,
+  .events[1] = ARMV8_PMUV3_BUS_ACCESS,
+  .events[2] = ARMV8_PMUV3_MEMORY_ERROR,
+  .n_events = 3,
+  .n_columns = 4,
+  .format_fn = format_arm_memory_access,
+  .column_headers = PERFMON_STRINGS ("Mem-access/pkt", "Bus-access/pkt",
+				     "Total-mem-errors", "pkts"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (SET_BIT (MEM_ACCESS),
+					  SET_BIT (BUS_ACCESS),
+					  SET_BIT (MEMORY_ERROR), 0),
+  .footer =
+    "Mem-access: The counter counts Memory-read operations and Memory-write"
+    " operations that the PE made\n"
+    "Bus-access: The counter counts Memory-read operations and Memory-write"
+    " operations that access outside of the boundary of the PE and its "
+    "closely-coupled caches\n"
+    "Mem-error: Memory error refers to a physical error in memory closely "
+    "coupled to this PE, and detected by the hardware, such as a parity or"
+    " ECC error\n"
+    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+    " event numbers for full description.\n"
+};
diff --git a/src/plugins/perfmon/arm/bundle/stall.c b/src/plugins/perfmon/arm/bundle/stall.c
new file mode 100644
index 00000000000..deef9045516
--- /dev/null
+++ b/src/plugins/perfmon/arm/bundle/stall.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2022 Arm and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <vppinfra/linux/sysfs.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/arm/events.h>
+
+/* as per .events[n] in PERFMON_REGISTER_BUNDLE */
+enum
+{
+  STALL_BACKEND,
+  STALL_FRONTEND
+};
+
+static u8 *
+format_arm_stall (u8 *s, va_list *args)
+{
+  perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
+  int row = va_arg (*args, int);
+
+  switch (row)
+    {
+    case 0:
+      s = format (s, "%llu", ns->value[STALL_BACKEND] / ns->n_packets);
+      break;
+
+    case 1:
+      s = format (s, "%llu", ns->value[STALL_FRONTEND] / ns->n_packets);
+      break;
+
+    case 2:
+      s = format (s, "%llu", ns->value[STALL_BACKEND] / ns->n_calls);
+      break;
+
+    case 3:
+      s = format (s, "%llu", ns->value[STALL_FRONTEND] / ns->n_calls);
+      break;
+
+    case 4:
+      s = format (s, "%llu", ns->n_packets);
+      break;
+
+    case 5:
+      s = format (s, "%llu", ns->n_calls);
+      break;
+    }
+  return s;
+}
+
+PERFMON_REGISTER_BUNDLE (arm_stall) = {
+  .name = "stall",
+  .description = "PE cycle stalls per pkt/call",
+  .source = "arm",
+  .type = PERFMON_BUNDLE_TYPE_NODE,
+  .events[0] = ARMV8_PMUV3_STALL_BACKEND,
+  .events[1] = ARMV8_PMUV3_STALL_FRONTEND,
+  .n_events = 2,
+  .n_columns = 6,
+  .format_fn = format_arm_stall,
+  .column_headers = PERFMON_STRINGS ("Backend/pkt", "Frontend/pkt",
+				     "Backend/call", "Frontend/call",
+				     "packets", "calls"),
+  /*
+   * set a bit for every event used in each column
+   * this allows us to disable columns at bundle registration if an
+   * event is not supported
+   */
+  .column_events = PERFMON_COLUMN_EVENTS (SET_BIT (STALL_BACKEND),
+					  SET_BIT (STALL_FRONTEND),
+					  SET_BIT (STALL_BACKEND),
+					  SET_BIT (STALL_FRONTEND), 0, 0),
+  .footer =
+    "The stall counter counts every Attributable cycle on which no\n"
+    "Attributable instruction or operation was sent for execution\n"
+    "on this PE.\n\n"
+    "     Stall backend: No operation issued due to the backend\n"
+    "     Stall frontend: No operation issued due to the frontend\n"
+    "The division between frontend and backend is IMPLEMENTATION DEFINED\n\n"
+    "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
+    " event numbers for full description.\n"
+};