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authorRay Kinsella <mdr@ashroe.eu>2021-10-15 12:48:31 +0100
committerDamjan Marion <dmarion@me.com>2021-10-16 08:32:43 +0000
commit0d27e3e7a1d5ddd572718818a56270bac639ea2e (patch)
tree16909b49fce3160d2ac5e9054103444db16dbd56 /src/plugins/perfmon/intel/core.h
parent5bb0eb122fa1a82abe0251903a91094a3a90603f (diff)
perfmon: topdown lvl 2 support on sapphire rapids
Added topdown level 2 support on sapphire rapids, including ability to indentify a sapphire rapids cpu. Type: improvement Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: I9f99a92fa0886b98bb5185cff32bebd5a094f329
Diffstat (limited to 'src/plugins/perfmon/intel/core.h')
-rw-r--r--src/plugins/perfmon/intel/core.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/plugins/perfmon/intel/core.h b/src/plugins/perfmon/intel/core.h
index 944331132f2..320d09fd7c5 100644
--- a/src/plugins/perfmon/intel/core.h
+++ b/src/plugins/perfmon/intel/core.h
@@ -30,7 +30,15 @@
_ (0x00, 0x82, 0, 0, 0, 0x00, TOPDOWN, L1_FE_BOUND_METRIC, \
"TMA fe bound slots for an unhalted logical processor.") \
_ (0x00, 0x83, 0, 0, 0, 0x00, TOPDOWN, L1_BE_BOUND_METRIC, \
- "TMA be bound slots for an unhalted logical processor.")
+ "TMA be bound slots for an unhalted logical processor.") \
+ _ (0x00, 0x84, 0, 0, 0, 0x00, TOPDOWN, L2_HEAVYOPS_METRIC, \
+ "TMA heavy operations for an unhalted logical processor.") \
+ _ (0x00, 0x85, 0, 0, 0, 0x00, TOPDOWN, L2_BMISPRED_METRIC, \
+ "TMA branch misprediction slots or an unhalted logical processor.") \
+ _ (0x00, 0x86, 0, 0, 0, 0x00, TOPDOWN, L2_FETCHLAT_METRIC, \
+ "TMA fetch latency slots for an unhalted logical processor.") \
+ _ (0x00, 0x87, 0, 0, 0, 0x00, TOPDOWN, L2_MEMBOUND_METRIC, \
+ "TMA mem bound slots for an unhalted logical processor.")
/* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
* counter_unit, name, suffix, description */