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authorRay Kinsella <mdr@ashroe.eu>2022-01-27 09:55:02 +0000
committerDamjan Marion <dmarion@me.com>2022-01-30 15:08:18 +0000
commit9d0c638b0fa28b9aebd9e3c0c0bdf98361d50a50 (patch)
tree58a696003ac68500a0824ad366a214d8305fbf53 /src/plugins/perfmon/intel/core.h
parent7e8aeb876b3bf21075621e40c3c1aa2fa2874dfb (diff)
perfmon: topdown level 1 and 2 for icx
Topdown level 1 and 2 for Intel Ice Lake (ICX). Limiting topdown support to THREAD for the moment on Ice Lake, as NODE support is still unreliable. Also removing Topdown Level 1 from Sapphire Rapids onwards, as Topdown LeveL 2 also shows Level 1 on Sapphire, and it reduces the overall number of bundles. Type: improvement Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: Iaa68b711dc8b6fb1090880b411debadb3c37f8bc
Diffstat (limited to 'src/plugins/perfmon/intel/core.h')
-rw-r--r--src/plugins/perfmon/intel/core.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/plugins/perfmon/intel/core.h b/src/plugins/perfmon/intel/core.h
index 971dc3465fa..108331674db 100644
--- a/src/plugins/perfmon/intel/core.h
+++ b/src/plugins/perfmon/intel/core.h
@@ -146,7 +146,10 @@
_ (0x83, 0x04, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_STALL, \
"Cycles where a code fetch is stalled due to L1 instruction cache tag " \
"miss.") \
- _ (0x9C, 0x01, 0, 0, 0, 0x00, IDQ_UOPS_NOT_DELIVERED, CORE, \
+ _ (0x83, 0x02, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_MISS, \
+ "Instruction fetch tag lookups that miss in the instruction cache " \
+ "(L1I). Counts at 64-byte cache-line granularity.") \
+ _ (0x9C, 0x01, 0, 0, 0, 0x05, IDQ_UOPS_NOT_DELIVERED, CORE, \
"Uops not delivered to Resource Allocation Table (RAT) per thread when " \
"backend of the machine is not stalled") \
_ (0xA1, 0x01, 0, 0, 0, 0x00, UOPS_DISPATCHED, PORT_0, \