diff options
| author |   Jieqiang Wang <jieqiang.wang@arm.com> | 2022-09-19 23:33:21 +0800 |
|---|---|---|
| committer |   Beno�t Ganne <bganne@cisco.com> | 2022-10-25 15:18:21 +0000 |
| commit | 186798270acb7e7c4159af982bb3f3dd5d9f50d0 (patch) | |
| tree | 523bc3177fa6b951a10dc1c078fe37bb4b003214 /src/plugins/rdma/rdma_mlx5dv.h | |
| parent | bf93670c515da131f36809091c13d3a0638fff2a (diff) | |
rdma: set correct CQE flags
CQE flags located in bits 16-31 at offset 0x1c should be defined as
actual numbers instead of indexes. Besides, L3 header type for IPv4 is
10(2 in decimal) and for IPv6 is 01(1 in decimal) according to CQE entry
fields description of page 120 in Mellanox Programmer Reference Manual.
(https://network.nvidia.com/files/doc-2020/ethernet-adapters-programming-manual.pdf)
Fixing this issue will lead to correct CQE flags printing for rdma-input
node when buffer trace is enabled.
Type: fix
Signed-off-by: Jieqiang Wang <jieqiang.wang@arm.com>
Change-Id: I9b578ca5cbd8cd93a577aa83131e31c79f60430e
Diffstat (limited to 'src/plugins/rdma/rdma_mlx5dv.h')
| -rw-r--r-- | src/plugins/rdma/rdma_mlx5dv.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/plugins/rdma/rdma_mlx5dv.h b/src/plugins/rdma/rdma_mlx5dv.h index efcefe7fbf7..bf01a3a37d6 100644 --- a/src/plugins/rdma/rdma_mlx5dv.h +++ b/src/plugins/rdma/rdma_mlx5dv.h @@ -24,16 +24,16 @@ #include <vppinfra/types.h> #include <vppinfra/error.h> /* CQE flags - bits 16-31 of qword at offset 0x1c */ -#define CQE_FLAG_L4_OK 10 -#define CQE_FLAG_L3_OK 9 -#define CQE_FLAG_L2_OK 8 -#define CQE_FLAG_IP_FRAG 7 +#define CQE_FLAG_L4_OK (1 << 10) +#define CQE_FLAG_L3_OK (1 << 9) +#define CQE_FLAG_L2_OK (1 << 8) +#define CQE_FLAG_IP_FRAG (1 << 7) #define CQE_FLAG_L4_HDR_TYPE(f) (((f) >> 4) & 7) #define CQE_FLAG_L3_HDR_TYPE_SHIFT (2) #define CQE_FLAG_L3_HDR_TYPE_MASK (3 << CQE_FLAG_L3_HDR_TYPE_SHIFT) #define CQE_FLAG_L3_HDR_TYPE(f) (((f) & CQE_FLAG_L3_HDR_TYPE_MASK) >> CQE_FLAG_L3_HDR_TYPE_SHIFT) -#define CQE_FLAG_L3_HDR_TYPE_IP4 1 -#define CQE_FLAG_L3_HDR_TYPE_IP6 2 +#define CQE_FLAG_L3_HDR_TYPE_IP4 2 +#define CQE_FLAG_L3_HDR_TYPE_IP6 1 #define CQE_FLAG_IP_EXT_OPTS 1 /* CQE byte count (Striding RQ) */ |