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| author |   Tianyu Li <tianyu.li@arm.com> | 2021-08-26 09:47:31 +0800 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2021-09-13 13:38:36 +0000 |
| commit | db79ac0502f3a2ecc20d4fa2e9f9be20bfb8e18c (patch) | |
| tree | cf8240b961c7601a6a5b100900bed540c1bb6fff /src/plugins/vrrp | |
| parent | 14b472e373228be0f4c96f5450f2ecd8aef4ac34 (diff) | |
dpdk: fix prefetch assert on Arm
CLIB_PREFETCH (cop[1], CLIB_CACHE_LINE_BYTES * 3, STORE);
Note on 64 bytes cache line size arm machines,
CLIB_CACHE_LINE_BYTES 128
CLIB_CACHE_PREFETCH_BYTES 6
above CLIB_PREFETCH () macro will be expand to
ASSERT ((size) <= 4 * CLIB_CACHE_PREFETCH_BYTES);
it will hit assert due to size (i.e. 3 * 128) > 4 * 64
Solution:
Change to CLIB_PREFETCH (cop[1], sizeof(*cop[1]), STORE);
Type: fix
Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Reviewed-by: Lijian Zhang <lijian.zhang@arm.com>
Change-Id: Id0981fd5bd2b25ff71db4197b25578d0b7a9803e
Diffstat (limited to 'src/plugins/vrrp')
0 files changed, 0 insertions, 0 deletions