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author | 2019-12-03 15:08:27 +0100 | |
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committer | 2019-12-04 18:08:51 +0000 | |
commit | c9cb8f6d9c6e1f51dfdf3e9f4ba0c9f38d1ca6d6 (patch) | |
tree | 88a0ebd269caeceb3dc1a7df4867d527455269ef /src/vcl/test/test_vcl.py | |
parent | d9577b4aa3a325e46c09796835d22122bec9e3d0 (diff) |
quic: fix stream tx_fifo race condition
Type: fix
There is a race condition in when receiving TX from
a client application :
As egress_emit writes as much data as possible to
the stream, if during egress_emit the app writes
to the fifo, the data will be directly passed to
quicly. Then TX callback happens and triggers
a scheduler update telling quilcy the stream has
data to send. When the next egress_emit is called
and no more data has come, we have nothing to write,
we return len = 0 to quicly which breaks an assert if
a loss happens later on.
Change-Id: I47e00a14dfc9068b5dac7b5c090a89124aea004f
Signed-off-by: Nathan Skrzypczak <nathan.skrzypczak@gmail.com>
Diffstat (limited to 'src/vcl/test/test_vcl.py')
0 files changed, 0 insertions, 0 deletions