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| author |   Zhiyong Yang <zhiyong.yang@intel.com> | 2019-05-05 22:52:43 +0800 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2019-05-06 16:33:49 +0000 |
| commit | 6fec8ea700c4789462748c91983e5adf4d60a266 (patch) | |
| tree | cda05d9fb97185f732f43b57df443d9119b936c7 /src/vcl | |
| parent | 0549378623484cc1d3f773669de4feed99a60019 (diff) | |
ip4_load_balance: leverage vlib_get_buffers
vlib_get_buffers can save 1.2 clocks/pkt from 16.1 to 14.9 clocks/pkt
on Skylake.
Change-Id: I79d8b58b192280af5e5a5f73562b6301e1821cec
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Diffstat (limited to 'src/vcl')
0 files changed, 0 insertions, 0 deletions