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| author |   Zhiyong Yang <zhiyong.yang@intel.com> | 2018-09-04 21:43:57 -0400 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2018-09-07 07:31:28 +0000 |
| commit | e4b202a4148e534927e7f6662f1de3be9d1a5583 (patch) | |
| tree | 4cc3f53ece6592061434e874687e8ab5711b5f74 /src/vcl | |
| parent | d9668e7153d92cfeee3eee08848426f762aa02a2 (diff) | |
geneve: fix variable initial value
It is not good enough to initialize sw_if_index0 = 0,
sw_if_index1 = 0, as it maybe causes the first two
incoming packets to miss necessary computation.
Change-Id: Ifcab408d9514820e0daa280f4c73956db13b59be
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Diffstat (limited to 'src/vcl')
0 files changed, 0 insertions, 0 deletions