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| author |   Damjan Marion <damarion@cisco.com> | 2018-06-28 17:55:50 +0200 |
|---|---|---|
| committer |   Marco Varlese <marco.varlese@suse.de> | 2018-06-29 07:46:33 +0000 |
| commit | 09fdf9d074430032c27aba9e12e52440c7de2006 (patch) | |
| tree | ac0e37d7a0181308d1408ce0f590f4e366faf06a /src/vlib/buffer_serialize.c | |
| parent | 697faeace706337eddf0407e4e28e0bb8d39c20e (diff) | |
bihash key compare improvements
Looks like CPU doesn't like overlaping loads.
This new codes in some cases shows 3-4 clock improvements.
Change-Id: Ia1b49976ad95140c573f892fdc0a32eebbfa06c8
Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vlib/buffer_serialize.c')
0 files changed, 0 insertions, 0 deletions