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| author |   Damjan Marion <damarion@cisco.com> | 2018-03-27 21:06:10 +0200 |
|---|---|---|
| committer | Damjan Marion <damarion@cisco.com> | 2018-03-27 21:06:21 +0200 |
| commit | be3f4d5a30d8b2acbcbe88f66b066597326aa42d (patch) | |
| tree | 7d8dfcb1e12c396df9f5355b1ff5c7cd0631d822 /src/vlib/main.h | |
| parent | 82f2e6e50dfedd495f8788f85b0f366f79ae8e1a (diff) | |
vlib: make cloned structures cacheline aligned
This address crash with gcc-7 observed when -o3 is used.
Change-Id: I10e87da8e5037ad480eba7fb0aaa9a657d3bf48d
Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vlib/main.h')
| -rw-r--r-- | src/vlib/main.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vlib/main.h b/src/vlib/main.h index 4e48d1de09c..57b1efb7513 100644 --- a/src/vlib/main.h +++ b/src/vlib/main.h @@ -58,6 +58,7 @@ typedef struct vlib_main_t { + CLIB_CACHE_LINE_ALIGN_MARK (cacheline0); /* Instruction level timing state. */ clib_time_t clib_time; |