diff options
| author |   Damjan Marion <damarion@cisco.com> | 2020-09-04 12:34:58 +0200 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2020-09-04 12:45:46 +0000 |
| commit | 0be1b764a3111a4107f81e42fba9cf99bf1c9baf (patch) | |
| tree | 46875ebf539cb468fa4d230c335b89643bf4cbbb /src/vlib | |
| parent | 93a7f63943ab6ed2460321f38c90246b1585f0c8 (diff) | |
buffers: improve cache occupancy
Adjust buffer allocation so it always have odd number of cache lines.
That should result in better distribution of cachelines among cache sets.
Type: improvement
Change-Id: I0d39d4cf01cff36ad6f70a700730823a96448c22
Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vlib')
| -rw-r--r-- | src/vlib/buffer.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/vlib/buffer.c b/src/vlib/buffer.c index a645438640a..17e7d24cb27 100644 --- a/src/vlib/buffer.c +++ b/src/vlib/buffer.c @@ -507,8 +507,14 @@ vlib_buffer_chain_append_data_with_alloc (vlib_main_t * vm, static uword vlib_buffer_alloc_size (uword ext_hdr_size, uword data_size) { - return CLIB_CACHE_LINE_ROUND (ext_hdr_size + sizeof (vlib_buffer_t) + - data_size); + uword alloc_size = ext_hdr_size + sizeof (vlib_buffer_t) + data_size; + alloc_size = CLIB_CACHE_LINE_ROUND (alloc_size); + + /* in case when we have even number of cachelines, we add one more for + * better cache occupancy */ + alloc_size |= CLIB_CACHE_LINE_BYTES; + + return alloc_size; } u8 |