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authorTianyu Li <tianyu.li@arm.com>2021-06-23 07:35:03 +0000
committerDamjan Marion <dmarion@me.com>2021-07-02 14:28:24 +0000
commit70b1cbdf2bd7687f840a59475ca769c9bab907c9 (patch)
tree911e87072e23cb58243293f126281b8613a50896 /src/vlib
parentecadf6a5395968092e093f7fa1d40a17762ebac1 (diff)
vlib: fix buffer pool alignment size
Alignment size should be CLIB_CACHE_LINE_BYTES(64) instead of CLIB_LOG2_CACHE_LINE_BYTES(6) Type: fix Signed-off-by: Tianyu Li <tianyu.li@arm.com> Change-Id: If2d5ae324093be64454377866297f5e76ccddc93
Diffstat (limited to 'src/vlib')
-rw-r--r--src/vlib/buffer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vlib/buffer.c b/src/vlib/buffer.c
index ae88b4e4d44..adaafa36f5d 100644
--- a/src/vlib/buffer.c
+++ b/src/vlib/buffer.c
@@ -509,7 +509,7 @@ vlib_buffer_pool_create (vlib_main_t * vm, char *name, u32 data_size,
if (vec_len (bm->buffer_pools) >= 255)
return ~0;
- vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_LOG2_CACHE_LINE_BYTES);
+ vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_CACHE_LINE_BYTES);
if (bm->buffer_mem_size == 0)
{