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author | Benoît Ganne <bganne@cisco.com> | 2021-07-07 14:58:06 +0200 |
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committer | Damjan Marion <dmarion@me.com> | 2021-08-20 11:25:27 +0000 |
commit | ea1f491314caaf083f1936fe099b974d4b284ba7 (patch) | |
tree | 02a769fa53df996acf417c287ab57bf0226d25e4 /src/vlib | |
parent | 42e2140dd97c0d03c7edc033119e1e1bb59ed5a5 (diff) |
rdma: decrease inlining
Remove aggressive inlining outside of the main loop to improve build
time (from 146s to 22s).
Type: refactor
Change-Id: I3824516a85b5e8d02894e66f19d891569c1a68fb
Signed-off-by: Benoît Ganne <bganne@cisco.com>
Diffstat (limited to 'src/vlib')
0 files changed, 0 insertions, 0 deletions