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authorFlorin Coras <fcoras@cisco.com>2019-08-02 12:52:00 -0700
committerDave Wallace <dwallacelf@gmail.com>2019-08-05 16:24:45 +0000
commit0048223baad2b58a4e91aaeb2d05886499bbe004 (patch)
treeb4990152bdda07f93b99e5fc75e4421353f53417 /src/vlibmemory
parent470b2a61659d76c1fc03352d42af6f3f3945330f (diff)
session: cache align transport base class
Type:refactor Also remove tx stats. Expectation is that transports will keep track of them. Change-Id: I083b328d87d0ad3688b630ddb5ef97827a4dbc2b Signed-off-by: Florin Coras <fcoras@cisco.com>
Diffstat (limited to 'src/vlibmemory')
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