diff options
| author |   Klement Sekera <ksekera@cisco.com> | 2019-11-21 10:31:03 +0000 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2019-11-26 09:54:29 +0000 |
| commit | 7dbf9a1a4fff5c3b20ad972289e49e3f88e82f2d (patch) | |
| tree | fbe9a1362abd78baa612da2c7d8a055c6f60c12f /src/vnet/adj/adj.h | |
| parent | 981a690b7d25c96ea56f95ece693377f95b93fc1 (diff) | |
fib: reduce save_rewrite_length to u8
This is a preparation step for migrating NAT to use SVR (shallow virtual
reassembly) to conserve space in vnet_buffer. Since max rewrite length
is currently pre-data size (128), u8 is sufficient to hold that value.
Type: refactor
Change-Id: I5374bb396e178245b870cb0bbf1370d2a54230bc
Signed-off-by: Klement Sekera <ksekera@cisco.com>
Diffstat (limited to 'src/vnet/adj/adj.h')
| -rw-r--r-- | src/vnet/adj/adj.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vnet/adj/adj.h b/src/vnet/adj/adj.h index 37389c346a0..9d1577fe911 100644 --- a/src/vnet/adj/adj.h +++ b/src/vnet/adj/adj.h @@ -316,7 +316,7 @@ typedef struct ip_adjacency_t_ CLIB_CACHE_LINE_ALIGN_MARK (cacheline1); /* Rewrite in second/third cache lines */ - vnet_declare_rewrite (VLIB_BUFFER_PRE_DATA_SIZE); + VNET_DECLARE_REWRITE; /** * more control plane members that do not fit on the first cacheline |