diff options
| author |   Lijian.Zhang <Lijian.Zhang@arm.com> | 2019-09-16 16:22:36 +0800 |
|---|---|---|
| committer |   Neale Ranns <nranns@cisco.com> | 2019-09-25 08:59:07 +0000 |
| commit | 33af8c1ed89f15cf0601ee891e9603bef16f2c93 (patch) | |
| tree | dfa3d9fe944cc1b12a5b4357067ed99e639a80d4 /src/vnet/adj/adj.h | |
| parent | 896c896a3c4ed563a270281ff8b50fd253f4833f (diff) | |
fib: fix some typos in fib/mtrie
Type: fix
Change-Id: I1af0e4a9bc23a3b6b6d3a74df093801ab6cae1f8
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Diffstat (limited to 'src/vnet/adj/adj.h')
| -rw-r--r-- | src/vnet/adj/adj.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/vnet/adj/adj.h b/src/vnet/adj/adj.h index 4c38b041b61..37389c346a0 100644 --- a/src/vnet/adj/adj.h +++ b/src/vnet/adj/adj.h @@ -216,14 +216,14 @@ extern u8* format_adj_flags(u8 * s, va_list * args); * @brief IP unicast adjacency. * @note cache aligned. * - * An adjacency is a represenation of a peer on a particular link. + * An adjacency is a representation of a peer on a particular link. */ typedef struct ip_adjacency_t_ { CLIB_CACHE_LINE_ALIGN_MARK (cacheline0); /** - * Linkage into the FIB node grpah. First member since this type + * Linkage into the FIB node graph. First member since this type * has 8 byte alignment requirements. */ fib_node_t ia_node; @@ -243,7 +243,7 @@ typedef struct ip_adjacency_t_ /** * The protocol of the neighbor/peer. i.e. the protocol with - * which to interpret the 'next-hop' attirbutes of the sub-types. + * which to interpret the 'next-hop' attributes of the sub-types. * 1-btyes */ fib_protocol_t ia_nh_proto; @@ -329,10 +329,10 @@ typedef struct ip_adjacency_t_ } ip_adjacency_t; STATIC_ASSERT ((STRUCT_OFFSET_OF (ip_adjacency_t, cacheline0) == 0), - "IP adjacency cachline 0 is not offset"); + "IP adjacency cacheline 0 is not offset"); STATIC_ASSERT ((STRUCT_OFFSET_OF (ip_adjacency_t, cacheline1) == CLIB_CACHE_LINE_BYTES), - "IP adjacency cachline 1 is more than one cachline size offset"); + "IP adjacency cacheline 1 is more than one cacheline size offset"); /** * @brief @@ -409,7 +409,7 @@ extern int adj_recursive_loop_detect (adj_index_t ai, /** * @brief - * The global adjacnecy pool. Exposed for fast/inline data-plane access + * The global adjacency pool. Exposed for fast/inline data-plane access */ extern ip_adjacency_t *adj_pool; |