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| author |   Lijian.Zhang <Lijian.Zhang@arm.com> | 2019-09-16 16:22:36 +0800 |
|---|---|---|
| committer |   Neale Ranns <nranns@cisco.com> | 2019-09-25 08:59:07 +0000 |
| commit | 33af8c1ed89f15cf0601ee891e9603bef16f2c93 (patch) | |
| tree | dfa3d9fe944cc1b12a5b4357067ed99e639a80d4 /src/vnet/dpo/load_balance.h | |
| parent | 896c896a3c4ed563a270281ff8b50fd253f4833f (diff) | |
fib: fix some typos in fib/mtrie
Type: fix
Change-Id: I1af0e4a9bc23a3b6b6d3a74df093801ab6cae1f8
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
Diffstat (limited to 'src/vnet/dpo/load_balance.h')
| -rw-r--r-- | src/vnet/dpo/load_balance.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vnet/dpo/load_balance.h b/src/vnet/dpo/load_balance.h index a204b7fdc58..5428e20e981 100644 --- a/src/vnet/dpo/load_balance.h +++ b/src/vnet/dpo/load_balance.h @@ -175,7 +175,7 @@ typedef struct load_balance_t_ { } load_balance_t; STATIC_ASSERT(sizeof(load_balance_t) <= CLIB_CACHE_LINE_BYTES, - "A load_balance object size exceeds one cachline"); + "A load_balance object size exceeds one cacheline"); /** * Flags controlling load-balance formatting/display |