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| author |   Lijian.Zhang <Lijian.Zhang@arm.com> | 2019-09-16 16:22:36 +0800 |
|---|---|---|
| committer |   Andrew Yourtchenko <ayourtch@gmail.com> | 2019-10-03 08:43:47 +0000 |
| commit | e8bcb944c5a83e55060b721aaf0e870754f756c3 (patch) | |
| tree | 66685d08e3d434e9a2d683fa7f3d719639f3d6b2 /src/vnet/dpo/load_balance.h | |
| parent | d46055e868b7e687f50866f8aa1cefc177836bc7 (diff) | |
fib: fix some typos in fib/mtrie
Type: fix
Change-Id: I1af0e4a9bc23a3b6b6d3a74df093801ab6cae1f8
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>
(cherry picked from commit 33af8c1ed89f15cf0601ee891e9603bef16f2c93)
Diffstat (limited to 'src/vnet/dpo/load_balance.h')
| -rw-r--r-- | src/vnet/dpo/load_balance.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vnet/dpo/load_balance.h b/src/vnet/dpo/load_balance.h index a204b7fdc58..5428e20e981 100644 --- a/src/vnet/dpo/load_balance.h +++ b/src/vnet/dpo/load_balance.h @@ -175,7 +175,7 @@ typedef struct load_balance_t_ { } load_balance_t; STATIC_ASSERT(sizeof(load_balance_t) <= CLIB_CACHE_LINE_BYTES, - "A load_balance object size exceeds one cachline"); + "A load_balance object size exceeds one cacheline"); /** * Flags controlling load-balance formatting/display |