Improve L2FIB PDR/NDR performance (VPP-963)

1. Limit MAC entry update per l2-learn call to reduce update burst
   when wall clock advance to the the next minute so all MAC time
   stamps are behind current time.
2. Optimize l2-learn node fast path code sequence.
3. Invalidate cache_key when update MAC entry.
4. Change L2 learn hit counter to L2 learn hit-update counter.
5. Increase L2FIB table memory size to 512MB to fit 4M entries
6. Set MAC learn limit at 4M entries

Change-Id: I19572f7f8a4b42a01be025a609fb03af50af16b2
Signed-off-by: John Lo <loj@cisco.com>

0 files changed, 0 insertions, 0 deletions