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authorZhiyong Yang <zhiyong.yang@intel.com>2018-11-07 00:04:28 -0500
committerDamjan Marion <dmarion@me.com>2018-11-15 17:20:28 +0000
commite01f6ef9efced0b89df4618a7f5e8894c70bbac7 (patch)
tree2ab79881aede6ed59d4f790834aa0ff094e568e7 /src/vnet
parentb4d3053445499a115f0f4debde6a8c7b29a8c071 (diff)
ip4-input: fix prefetch data issue for tunnel decap cases
There are two reasons to modify the existing code ip4_input_inline. 1. For many tunnel decap cases, inner ip header or its part is possible in the second cacheline, not first cacheline only after the field "data", and this will cause data cache miss once the second cacheline is needed to access. e.g vxlan-gpe. 2. For most of cases, "data" is the starting address of ethernet header, not IP header. The existing code causes misunderstanding from code readability perspective. Change-Id: I43e119b899dbde95803bccbac54259729fd2cddf Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com> Signed-off-by: Yuwei Zhang <yuwei1.zhang@intel.com>
Diffstat (limited to 'src/vnet')
-rw-r--r--src/vnet/ip/ip4_input.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/vnet/ip/ip4_input.c b/src/vnet/ip/ip4_input.c
index 5a2ae17391f..1928a66d76c 100644
--- a/src/vnet/ip/ip4_input.c
+++ b/src/vnet/ip/ip4_input.c
@@ -163,10 +163,14 @@ ip4_input_inline (vlib_main_t * vm,
vlib_prefetch_buffer_header (b[10], LOAD);
vlib_prefetch_buffer_header (b[11], LOAD);
- CLIB_PREFETCH (b[4]->data, sizeof (ip4_header_t), LOAD);
- CLIB_PREFETCH (b[5]->data, sizeof (ip4_header_t), LOAD);
- CLIB_PREFETCH (b[6]->data, sizeof (ip4_header_t), LOAD);
- CLIB_PREFETCH (b[7]->data, sizeof (ip4_header_t), LOAD);
+ CLIB_PREFETCH (vlib_buffer_get_current (b[4]),
+ sizeof (ip4_header_t), LOAD);
+ CLIB_PREFETCH (vlib_buffer_get_current (b[5]),
+ sizeof (ip4_header_t), LOAD);
+ CLIB_PREFETCH (vlib_buffer_get_current (b[6]),
+ sizeof (ip4_header_t), LOAD);
+ CLIB_PREFETCH (vlib_buffer_get_current (b[7]),
+ sizeof (ip4_header_t), LOAD);
}
vnet_buffer (b[0])->ip.adj_index[VLIB_RX] = ~0;