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authorDamjan Marion <damarion@cisco.com>2018-06-28 17:55:50 +0200
committerMarco Varlese <marco.varlese@suse.de>2018-06-29 07:46:33 +0000
commit09fdf9d074430032c27aba9e12e52440c7de2006 (patch)
treeac0e37d7a0181308d1408ce0f590f4e366faf06a /src/vppinfra/bihash_24_8.h
parent697faeace706337eddf0407e4e28e0bb8d39c20e (diff)
bihash key compare improvements
Looks like CPU doesn't like overlaping loads. This new codes in some cases shows 3-4 clock improvements. Change-Id: Ia1b49976ad95140c573f892fdc0a32eebbfa06c8 Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vppinfra/bihash_24_8.h')
-rw-r--r--src/vppinfra/bihash_24_8.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/vppinfra/bihash_24_8.h b/src/vppinfra/bihash_24_8.h
index 0c57e35bc47..dcce2a21259 100644
--- a/src/vppinfra/bihash_24_8.h
+++ b/src/vppinfra/bihash_24_8.h
@@ -72,9 +72,8 @@ clib_bihash_key_compare_24_8 (u64 * a, u64 * b)
u64x8 v = u64x8_load_unaligned (a) ^ u64x8_load_unaligned (b);
return (u64x8_is_zero_mask (v) & 0x7) == 0;
#elif defined(CLIB_HAVE_VEC128) && defined(CLIB_HAVE_VEC128_UNALIGNED_LOAD_STORE)
- u64x2 v;
- v = u64x2_load_unaligned (a) ^ u64x2_load_unaligned (b);
- v |= u64x2_load_unaligned (a + 1) ^ u64x2_load_unaligned (b + 1);
+ u64x2 v = { a[2] ^ b[2], 0 };
+ v |= u64x2_load_unaligned (a) ^ u64x2_load_unaligned (b);
return u64x2_is_all_zero (v);
#else
return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;