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authorBenoît Ganne <bganne@cisco.com>2019-12-16 10:42:25 +0100
committerDamjan Marion <dmarion@me.com>2020-03-16 19:09:39 +0000
commitdc812d9a71f2f5105e4aaba50fd98ea3b0b50a9b (patch)
tree0a6db468c41b164e1a71bbebc613e6b469c617c3 /src/vppinfra/clib.h
parentdd648aac0615c416507de9097b6f50db16ad319c (diff)
rdma: introduce direct verb for Cx4/5 tx
Direct Verb allows for direct access to NIC HW rx/tx rings. This patch introduce TX direct verb support for Mellanox ConnectX-4/5 adapters. 'dv' mode must be explicitely selected at interface creation to benefit from this. Type: feature Change-Id: If830ba9f33db73299acdbddc68b5c09eaf6add98 Signed-off-by: Benoît Ganne <bganne@cisco.com>
Diffstat (limited to 'src/vppinfra/clib.h')
-rw-r--r--src/vppinfra/clib.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/vppinfra/clib.h b/src/vppinfra/clib.h
index 8aec1f16beb..dac41adb165 100644
--- a/src/vppinfra/clib.h
+++ b/src/vppinfra/clib.h
@@ -111,6 +111,14 @@
#define PREDICT_FALSE(x) __builtin_expect((x),0)
#define PREDICT_TRUE(x) __builtin_expect((x),1)
+/*
+ * Compiler barrier
+ * prevent compiler to reorder memory access accross this boundary
+ * prevent compiler to cache values in register (force reload)
+ * Not to be confused with CPU memory barrier below
+ */
+#define CLIB_COMPILER_BARRIER() asm volatile ("":::"memory")
+
/* Full memory barrier (read and write). */
#define CLIB_MEMORY_BARRIER() __sync_synchronize ()