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| author |   Yulong Pei <yulong.pei@intel.com> | 2018-10-19 23:29:29 +0800 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2018-11-06 12:05:40 +0000 |
| commit | dcb0c1aae89a8b542f734b89e33505852ab3d6da (patch) | |
| tree | 8b9ab1cd8e9d3ea79d4f99b3a4889bbef97d0c65 /src/vppinfra/clib_error.h | |
| parent | f286c4b9427748568036d04e8aa2408a4069dee7 (diff) | |
Change l2_patch from dual-loop to quad-loop
The change can save 1.1 clocks per packet on Intel Atom C3858 platform,
It downgraded from 2.05e1 to 1.94e1 clocks per packet.
The change can save 0.3 clocks per packet on Intel Xeon CPU E5-2699 v4 @ 2.20GHz,
It downgraded from 1.26e1 to 1.23e1 clocks per packet.
Change-Id: I1ede77fb592a797d86940a8abad9ca291a89f1c7
Signed-off-by: Yulong Pei <yulong.pei@intel.com>
Diffstat (limited to 'src/vppinfra/clib_error.h')
0 files changed, 0 insertions, 0 deletions