diff options
| author |   Damjan Marion <damarion@cisco.com> | 2023-09-12 15:08:58 +0200 |
|---|---|---|
| committer |   Dave Wallace <dwallacelf@gmail.com> | 2023-09-13 15:02:43 +0000 |
| commit | 7bf8f5e484a49fd90db1c4c4e38d82810bddada8 (patch) | |
| tree | 8f7b10dd9fe95eaadfcc591af3ac69be03b66546 /src/vppinfra/cpu.c | |
| parent | 3d2f718e6fece410a903474741487fdff9d5cb27 (diff) | |
vppinfra: add ARM Neoverse-N2 support
Type: improvement
Change-Id: Ief77ae7338667ede290aece6933bb5ae2e76ffc6
Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vppinfra/cpu.c')
| -rw-r--r-- | src/vppinfra/cpu.c | 74 |
1 files changed, 52 insertions, 22 deletions
diff --git a/src/vppinfra/cpu.c b/src/vppinfra/cpu.c index b66dd4968ad..79e7dc0955e 100644 --- a/src/vppinfra/cpu.c +++ b/src/vppinfra/cpu.c @@ -71,21 +71,22 @@ _ (0x06, 0x17, "Penryn", "Yorkfield,Wolfdale,Penryn,Harpertown") /* _(implementor-id, part-id, vendor-name, cpu-name, show CPU pass as string) */ -#define foreach_aarch64_cpu_uarch \ - _(0x41, 0xd03, "ARM", "Cortex-A53", 0) \ - _(0x41, 0xd07, "ARM", "Cortex-A57", 0) \ - _(0x41, 0xd08, "ARM", "Cortex-A72", 0) \ - _(0x41, 0xd09, "ARM", "Cortex-A73", 0) \ - _(0x41, 0xd0a, "ARM", "Cortex-A75", 0) \ - _(0x41, 0xd0b, "ARM", "Cortex-A76", 0) \ - _(0x41, 0xd0c, "ARM", "Neoverse-N1", 0) \ - _(0x41, 0xd4a, "ARM", "Neoverse-E1", 0) \ - _(0x43, 0x0a1, "Marvell", "THUNDERX CN88XX", 0) \ - _(0x43, 0x0a2, "Marvell", "OCTEON TX CN81XX", 0) \ - _(0x43, 0x0a3, "Marvell", "OCTEON TX CN83XX", 0) \ - _(0x43, 0x0af, "Marvell", "THUNDERX2 CN99XX", 1) \ - _(0x43, 0x0b1, "Marvell", "OCTEON TX2 CN98XX", 1) \ - _(0x43, 0x0b2, "Marvell", "OCTEON TX2 CN96XX", 1) +#define foreach_aarch64_cpu_uarch \ + _ (0x41, 0xd03, "ARM", "Cortex-A53", 0) \ + _ (0x41, 0xd07, "ARM", "Cortex-A57", 0) \ + _ (0x41, 0xd08, "ARM", "Cortex-A72", 0) \ + _ (0x41, 0xd09, "ARM", "Cortex-A73", 0) \ + _ (0x41, 0xd0a, "ARM", "Cortex-A75", 0) \ + _ (0x41, 0xd0b, "ARM", "Cortex-A76", 0) \ + _ (0x41, 0xd0c, "ARM", "Neoverse-N1", 0) \ + _ (0x41, 0xd49, "ARM", "Neoverse-N2", 0) \ + _ (0x41, 0xd4a, "ARM", "Neoverse-E1", 0) \ + _ (0x43, 0x0a1, "Marvell", "THUNDERX CN88XX", 0) \ + _ (0x43, 0x0a2, "Marvell", "OCTEON TX CN81XX", 0) \ + _ (0x43, 0x0a3, "Marvell", "OCTEON TX CN83XX", 0) \ + _ (0x43, 0x0af, "Marvell", "THUNDERX2 CN99XX", 1) \ + _ (0x43, 0x0b1, "Marvell", "OCTEON TX2 CN98XX", 1) \ + _ (0x43, 0x0b2, "Marvell", "OCTEON TX2 CN96XX", 1) __clib_export u8 * format_cpu_uarch (u8 * s, va_list * args) @@ -276,10 +277,39 @@ format_march_variant (u8 *s, va_list *args) return format (s, "%s", variants[t]); } -/* - * fd.io coding-style-patch-verification: ON - * - * Local Variables: - * eval: (c-set-style "gnu") - * End: - */ +#ifdef __aarch64__ + +__clib_export const clib_cpu_info_t * +clib_get_cpu_info () +{ + static int first_run = 1; + static clib_cpu_info_t info = {}; + if (first_run) + { + FILE *fp = fopen ("/proc/cpuinfo", "r"); + char buf[128]; + + if (!fp) + return 0; + + while (!feof (fp)) + { + if (!fgets (buf, sizeof (buf), fp)) + break; + buf[127] = '\0'; + if (strstr (buf, "CPU part")) + info.aarch64.part_num = + strtol (memchr (buf, ':', 128) + 2, NULL, 0); + + if (strstr (buf, "CPU implementer")) + info.aarch64.implementer = + strtol (memchr (buf, ':', 128) + 2, NULL, 0); + } + fclose (fp); + + first_run = 0; + } + return &info; +} + +#endif |