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authorRay Kinsella <mdr@ashroe.eu>2021-10-15 12:48:31 +0100
committerDamjan Marion <dmarion@me.com>2021-10-16 08:32:43 +0000
commit0d27e3e7a1d5ddd572718818a56270bac639ea2e (patch)
tree16909b49fce3160d2ac5e9054103444db16dbd56 /src/vppinfra/cpu.h
parent5bb0eb122fa1a82abe0251903a91094a3a90603f (diff)
perfmon: topdown lvl 2 support on sapphire rapids
Added topdown level 2 support on sapphire rapids, including ability to indentify a sapphire rapids cpu. Type: improvement Signed-off-by: Ray Kinsella <mdr@ashroe.eu> Change-Id: I9f99a92fa0886b98bb5185cff32bebd5a094f329
Diffstat (limited to 'src/vppinfra/cpu.h')
-rw-r--r--src/vppinfra/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vppinfra/cpu.h b/src/vppinfra/cpu.h
index c1f2e9e8248..50d8b61cab3 100644
--- a/src/vppinfra/cpu.h
+++ b/src/vppinfra/cpu.h
@@ -134,6 +134,7 @@ _CLIB_MARCH_FN_REGISTRATION(fn)
_ (avx512_vpopcntdq, 7, ecx, 14) \
_ (movdiri, 7, ecx, 27) \
_ (movdir64b, 7, ecx, 28) \
+ _ (avx512_fp16, 7, edx, 23) \
_ (invariant_tsc, 0x80000007, edx, 8)
#define foreach_aarch64_flags \