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authorDamjan Marion <damarion@cisco.com>2023-03-15 11:08:53 +0000
committerDamjan Marion <damarion@cisco.com>2023-03-15 11:10:24 +0000
commit1ca681838c939135b067b2db79b0c540fd803e37 (patch)
treee71b31b614746d5f804a2c162507033cec19b4f0 /src/vppinfra/cpu.h
parent6a6df00abcb8dd98d4793f4dca114b97a7c48354 (diff)
build: add support for intel alderlake and sapphirerapids, part 2
Type: improvement Change-Id: I64ca5bd3a959190111f61c5311a908d242c10bad Signed-off-by: Damjan Marion <damarion@cisco.com>
Diffstat (limited to 'src/vppinfra/cpu.h')
-rw-r--r--src/vppinfra/cpu.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/vppinfra/cpu.h b/src/vppinfra/cpu.h
index efa85ad1af1..a30401ab371 100644
--- a/src/vppinfra/cpu.h
+++ b/src/vppinfra/cpu.h
@@ -24,7 +24,9 @@
_ (hsw, "Intel Haswell") \
_ (trm, "Intel Tremont") \
_ (skx, "Intel Skylake (server) / Cascade Lake") \
- _ (icl, "Intel Ice Lake")
+ _ (icl, "Intel Ice Lake") \
+ _ (adl, "Intel Alder Lake") \
+ _ (spr, "Intel Sapphire Rapids")
#elif defined(__aarch64__)
#define foreach_march_variant \
_ (octeontx2, "Marvell Octeon TX2") \