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| author |   Neale Ranns <nranns@cisco.com> | 2019-05-22 13:26:39 +0000 |
|---|---|---|
| committer |   Damjan Marion <dmarion@me.com> | 2019-06-05 11:33:12 +0000 |
| commit | 59fa121f8953f7b07f0cc02149ca28182f959f42 (patch) | |
| tree | 51249a3bf2da047a791b7446af09f15df91118a6 /src/vppinfra/tw_timer_1t_3w_1024sl_ov.h | |
| parent | e6be702362299566990678f505512b1b74b49112 (diff) | |
L3 cross connect
- all packets input on interface X are load-balanced over the set of
paths provided.
Change-Id: Ic27cb88c4cd5d6d3462570632daff7a43d5a652d
Signed-off-by: Neale Ranns <nranns@cisco.com>
Diffstat (limited to 'src/vppinfra/tw_timer_1t_3w_1024sl_ov.h')
0 files changed, 0 insertions, 0 deletions