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authorLijian Zhang <Lijian.Zhang@arm.com>2018-09-10 17:13:56 +0800
committerDamjan Marion <dmarion@me.com>2018-10-01 09:28:41 +0000
commit2e2372117d35191a0e6c096c5f989930de6e12b1 (patch)
tree16ba106360c4bda39b78ee02f515cbbb2c284e0f /src/vppinfra
parent88c6e0086b15963b4d1a268e1fe8bbc2bcd9779c (diff)
Support dynamic dual/quad loop selection on aarch64
Currently, there are three variants available on aarch64, qdf24xx, thunderx2t99, and cortex-a72. -DCLIB_N_PREFETCHES is passed to source code to select dual/quad implementation. Besides, different compiler options are applied on these critical functions. gcc-7.3.0 reports ICE(internal compiler error) with -mtune=thunderx2t99, so -mtune=thunderx2t99 is enabled only when gcc version is greater than 7.3.0 Cavium ThunderX2, Impermenter 0x43, Part 0x0af -march=armv8-a+crc+crypto -mtune=thunderx2t99 Qualcomm Centriq 2400, Impermenter 0x51, Part 0xc00 -march=armv8.1-a+crc+crypto -mtune=qdf24xx Cortex-A72, Impermenter 0x41, Part 0xd08 -march=armv8-a+crc+crypto -mtune=cortex-a72 Change-Id: Id5649c6325c1e642d0fd42535e3908793b13e02a Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com> Reviewed-by: Sirshak Das <sirshak.das@arm.com> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
Diffstat (limited to 'src/vppinfra')
-rw-r--r--src/vppinfra/cache.h5
-rw-r--r--src/vppinfra/cpu.h90
2 files changed, 95 insertions, 0 deletions
diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index 7a54d34dfee..e8e89ba8556 100644
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -59,6 +59,11 @@
#define CLIB_CACHE_LINE_BYTES (1 << CLIB_LOG2_CACHE_LINE_BYTES)
#define CLIB_CACHE_LINE_ALIGN_MARK(mark) u8 mark[0] __attribute__((aligned(CLIB_CACHE_LINE_BYTES)))
+/* Default cache line fill buffers. */
+#ifndef CLIB_N_PREFETCHES
+#define CLIB_N_PREFETCHES 16
+#endif
+
/* Read/write arguments to __builtin_prefetch. */
#define CLIB_PREFETCH_READ 0
#define CLIB_PREFETCH_LOAD 0 /* alias for read */
diff --git a/src/vppinfra/cpu.h b/src/vppinfra/cpu.h
index c636cf8639c..0ca9edb97fc 100644
--- a/src/vppinfra/cpu.h
+++ b/src/vppinfra/cpu.h
@@ -183,6 +183,96 @@ clib_cpu_march_priority_avx2 ()
return -1;
}
+static inline u32
+clib_cpu_implementer ()
+{
+ char buf[128];
+ static u32 implementer = -1;
+
+ if (-1 != implementer)
+ return implementer;
+
+ FILE *fp = fopen ("/proc/cpuinfo", "r");
+ if (!fp)
+ return implementer;
+
+ while (!feof (fp))
+ {
+ if (!fgets (buf, sizeof (buf), fp))
+ break;
+ buf[127] = '\0';
+ if (strstr (buf, "CPU implementer"))
+ implementer = (u32) strtol (memchr (buf, ':', 128) + 2, NULL, 0);
+ if (-1 != implementer)
+ break;
+ }
+ fclose (fp);
+
+ return implementer;
+}
+
+static inline u32
+clib_cpu_part ()
+{
+ char buf[128];
+ static u32 part = -1;
+
+ if (-1 != part)
+ return part;
+
+ FILE *fp = fopen ("/proc/cpuinfo", "r");
+ if (!fp)
+ return part;
+
+ while (!feof (fp))
+ {
+ if (!fgets (buf, sizeof (buf), fp))
+ break;
+ buf[127] = '\0';
+ if (strstr (buf, "CPU part"))
+ part = (u32) strtol (memchr (buf, ':', 128) + 2, NULL, 0);
+ if (-1 != part)
+ break;
+ }
+ fclose (fp);
+
+ return part;
+}
+
+#define AARCH64_CPU_IMPLEMENTER_THUNERDERX2 0x43
+#define AARCH64_CPU_PART_THUNERDERX2 0x0af
+#define AARCH64_CPU_IMPLEMENTER_QDF24XX 0x51
+#define AARCH64_CPU_PART_QDF24XX 0xc00
+#define AARCH64_CPU_IMPLEMENTER_CORTEXA72 0x41
+#define AARCH64_CPU_PART_CORTEXA72 0xd08
+
+static inline int
+clib_cpu_march_priority_thunderx2t99 ()
+{
+ if ((AARCH64_CPU_IMPLEMENTER_THUNERDERX2 == clib_cpu_implementer ()) &&
+ (AARCH64_CPU_PART_THUNERDERX2 == clib_cpu_part ()))
+ return 20;
+ return -1;
+}
+
+static inline int
+clib_cpu_march_priority_qdf24xx ()
+{
+ if ((AARCH64_CPU_IMPLEMENTER_QDF24XX == clib_cpu_implementer ()) &&
+ (AARCH64_CPU_PART_QDF24XX == clib_cpu_part ()))
+ return 20;
+ return -1;
+}
+
+static inline int
+clib_cpu_march_priority_cortexa72 ()
+{
+ if ((AARCH64_CPU_IMPLEMENTER_CORTEXA72 == clib_cpu_implementer ()) &&
+ (AARCH64_CPU_PART_CORTEXA72 == clib_cpu_part ()))
+ return 10;
+ return -1;
+}
+
#ifdef CLIB_MARCH_VARIANT
#define CLIB_MARCH_FN_PRIORITY() CLIB_MARCH_SFX(clib_cpu_march_priority)()
#else