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authorLeyi Rong <leyi.rong@intel.com>2023-03-08 13:34:56 +0800
committerDamjan Marion <dmarion@0xa5.net>2023-03-10 15:57:09 +0000
commit767a9ab4b1f77760a633ba3de30a0dcad44cb4b1 (patch)
treedc742984919960e2dda931734ae2650ce2b5f451 /src/vppinfra
parent7b0d48fbb3ceebcafb18177fba02ab1a9ad4c24e (diff)
vlib: 512-bit SIMD version of vlib_buffer_free
Process 8 packets perf batch in vlib_buffer_free_inline() when CLIB_HAVE_VEC512 is enabled. Type: improvement Signed-off-by: Leyi Rong <leyi.rong@intel.com> Change-Id: I78b8a525bce25ee355c9bf0e0f651698a8c45bda
Diffstat (limited to 'src/vppinfra')
-rw-r--r--src/vppinfra/vector/index_to_ptr.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/vppinfra/vector/index_to_ptr.h b/src/vppinfra/vector/index_to_ptr.h
index 91de3546439..3985b757d54 100644
--- a/src/vppinfra/vector/index_to_ptr.h
+++ b/src/vppinfra/vector/index_to_ptr.h
@@ -92,7 +92,7 @@ clib_index_to_ptr_u32 (u32 *indices, void *base, u8 shift, void **ptrs,
indices += 16;
n_elts -= 16;
}
- if (n_elts > 8)
+ if (n_elts >= 8)
{
b0 = u64x8_from_u32x8 (u32x8_load_unaligned (indices));
u64x8_store_unaligned ((b0 << shift) + off, ptrs);
@@ -101,6 +101,9 @@ clib_index_to_ptr_u32 (u32 *indices, void *base, u8 shift, void **ptrs,
n_elts -= 8;
}
+ if (n_elts == 0)
+ return;
+
b0 = u64x8_from_u32x8 (u32x8_load_unaligned (indices + n_elts - 8));
u64x8_store_unaligned ((b0 << shift) + off, ptrs + n_elts - 8);
}