perfmon: Topdown Level 1 support on Snowridge

Enable Topdown Level 1 support on Snowridge,
enabled with standard CPU events on small core.

Type: improvement

Signed-off-by: Ray Kinsella <mdr@ashroe.eu>
Change-Id: I58ad09383de7464265ac1b69e683f253591e3b5e

4 files changed, 102 insertions, 1 deletions

diff --git a/src/plugins/perfmon/CMakeLists.txt b/src/plugins/perfmon/CMakeLists.txt
index 060c425df4d..c587e6d503b 100644
--- a/src/plugins/perfmon/CMakeLists.txt
+++ b/src/plugins/perfmon/CMakeLists.txt
@@ -31,6 +31,7 @@ add_vpp_plugin(perfmon
   intel/bundle/branch_mispred.c
   intel/bundle/power_license.c
   intel/bundle/topdown_metrics.c
+  intel/bundle/topdown_tremont.c
 
   COMPONENT
   vpp-plugin-devtools
diff --git a/src/plugins/perfmon/intel/bundle/topdown_tremont.c b/src/plugins/perfmon/intel/bundle/topdown_tremont.c
new file mode 100644
index 00000000000..b2626eb0480
--- /dev/null
+++ b/src/plugins/perfmon/intel/bundle/topdown_tremont.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021 Intel and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <vnet/vnet.h>
+#include <perfmon/perfmon.h>
+#include <perfmon/intel/core.h>
+
+typedef enum
+{
+  TOPDOWN_E_RETIRING = 0,
+  TOPDOWN_E_BAD_SPEC,
+  TOPDOWN_E_FE_BOUND,
+  TOPDOWN_E_BE_BOUND,
+  TOPDOWN_E_MAX,
+} topdown_lvl1_t;
+
+static u8 *
+format_topdown_lvl1 (u8 *s, va_list *args)
+{
+  perfmon_reading_t *ss = va_arg (*args, perfmon_reading_t *);
+  u64 idx = va_arg (*args, int);
+  f64 sv = 0;
+  u64 total = 0;
+
+  for (int i = 0; i < TOPDOWN_E_MAX; i++)
+    total += ss->value[i];
+
+  switch (idx)
+    {
+    case 0:
+      sv = (f64) ss->value[TOPDOWN_E_RETIRING] + ss->value[TOPDOWN_E_BAD_SPEC];
+      break;
+    case 1:
+      sv = (f64) ss->value[TOPDOWN_E_FE_BOUND] + ss->value[TOPDOWN_E_BE_BOUND];
+      break;
+    default:
+      sv = (f64) ss->value[idx - 2];
+      break;
+    }
+
+  sv = (sv / total) * 100;
+  s = format (s, "%f", sv);
+  return s;
+}
+
+static int
+is_tremont ()
+{
+  return clib_cpu_supports_movdir64b () && !clib_cpu_supports_avx2 ();
+}
+
+static perfmon_cpu_supports_t topdown_lvl1_cpu_supports[] = {
+  { is_tremont, PERFMON_BUNDLE_TYPE_THREAD }
+};
+
+PERFMON_REGISTER_BUNDLE (topdown_lvl1_tremont) = {
+  .name = "topdown-level1",
+  .description = "Top-down Microarchitecture Analysis Level 1",
+  .source = "intel-core",
+  .events[0] = INTEL_CORE_E_TOPDOWN_L1_RETIRING_TREMONT,
+  .events[1] = INTEL_CORE_E_TOPDOWN_L1_BAD_SPEC_TREMONT,
+  .events[2] = INTEL_CORE_E_TOPDOWN_L1_FE_BOUND_TREMONT,
+  .events[3] = INTEL_CORE_E_TOPDOWN_L1_BE_BOUND_TREMONT,
+  .n_events = 4,
+  .cpu_supports = topdown_lvl1_cpu_supports,
+  .n_cpu_supports = ARRAY_LEN (topdown_lvl1_cpu_supports),
+  .format_fn = format_topdown_lvl1,
+  .column_headers = PERFMON_STRINGS ("% NS", "% ST", "% NS.RT", "% NS.BS",
+				     "% ST.FE", "% ST.BE"),
+  .footer = "Not Stalled (NS),STalled (ST),\n"
+	    " Retiring (RT), Bad Speculation (BS),\n"
+	    " FrontEnd bound (FE), BackEnd bound (BE)",
+};
diff --git a/src/plugins/perfmon/intel/core.c b/src/plugins/perfmon/intel/core.c
index 5e90c00eb38..c931c127f67 100644
--- a/src/plugins/perfmon/intel/core.c
+++ b/src/plugins/perfmon/intel/core.c
@@ -28,6 +28,8 @@ static perfmon_event_t events[] = {
 				    .exclude_kernel = 1 },
 
   foreach_perf_intel_core_event foreach_perf_intel_peusdo_event
+    foreach_perf_intel_tremont_event
+
 #undef _
 };
 
diff --git a/src/plugins/perfmon/intel/core.h b/src/plugins/perfmon/intel/core.h
index d2960b12401..944331132f2 100644
--- a/src/plugins/perfmon/intel/core.h
+++ b/src/plugins/perfmon/intel/core.h
@@ -34,6 +34,18 @@
 
 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
  * counter_unit, name, suffix, description */
+#define foreach_perf_intel_tremont_event                                      \
+  _ (0xc2, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_RETIRING_TREMONT,                 \
+     "TMA retiring slots for an unhalted logical processor.")                 \
+  _ (0x71, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_FE_BOUND_TREMONT,                 \
+     "TMA fe bound slots for an unhalted logical processor.")                 \
+  _ (0x73, 0x06, 0, 0, 0, 0x00, TOPDOWN, L1_BAD_SPEC_TREMONT,                 \
+     "TMA bad spec slots or an unhalted logical processor.")                  \
+  _ (0x74, 0x00, 0, 0, 0, 0x00, TOPDOWN, L1_BE_BOUND_TREMONT,                 \
+     "TMA be bound slots for an unhalted logical processor.")
+
+/* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
+ * counter_unit, name, suffix, description */
 #define foreach_perf_intel_core_event                                         \
   _ (0x00, 0x02, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD,                     \
      "Core cycles when the thread is not in halt state")                      \
@@ -197,8 +209,9 @@ typedef enum
 #define _(event, umask, edge, any, inv, cmask, name, suffix, desc)            \
   INTEL_CORE_E_##name##_##suffix,
   foreach_perf_intel_core_event foreach_perf_intel_peusdo_event
+    foreach_perf_intel_tremont_event
 #undef _
-    INTEL_CORE_N_EVENTS,
+      INTEL_CORE_N_EVENTS,
 } perf_intel_core_event_t;
 
 #endif