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authorLijian.Zhang <Lijian.Zhang@arm.com>2019-05-29 17:08:47 +0800
committerLijian.Zhang <Lijian.Zhang@arm.com>2019-06-21 11:27:33 +0800
commit107aa83630a1943018a4f96eb235ba8981748568 (patch)
tree559c6e87d667abe7bcdb83000729bbfceb494c5d /src
parent07beadedea9b23d97e41b3090590326c18151c66 (diff)
vppinfra: add u64x2_gather/u32x4_gather
Add u64x2_gather/u32x4_gather in vector_neon.h. u64x2_gather/u32x4_gather gathers data from scattered memory locations to a SIMD register. Type: feature Change-Id: I1dd27e38af28b9bed85143014c86197ee549fede Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com> Reviewed-by: Sirshak Das <Sirshak.Das@arm.com> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/vppinfra/vector_neon.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/vppinfra/vector_neon.h b/src/vppinfra/vector_neon.h
index 37bd1bb0b01..4e911ac678a 100644
--- a/src/vppinfra/vector_neon.h
+++ b/src/vppinfra/vector_neon.h
@@ -142,6 +142,24 @@ u8x16_msb_mask (u8x16 v)
return (u16) (vgetq_lane_u64 (x64, 0) + (vgetq_lane_u64 (x64, 1) << 8));
}
+static_always_inline u64x2
+u64x2_gather (void *p0, void *p1)
+{
+ u64x2 r = vdupq_n_u64 (*(u64 *) p0);
+ r = vsetq_lane_u64 (*(u64 *) p1, r, 1);
+ return r;
+}
+
+static_always_inline u32x4
+u32x4_gather (void *p0, void *p1, void *p2, void *p3)
+{
+ u32x4 r = vdupq_n_u32 (*(u32 *) p0);
+ r = vsetq_lane_u32 (*(u32 *) p1, r, 1);
+ r = vsetq_lane_u32 (*(u32 *) p2, r, 2);
+ r = vsetq_lane_u32 (*(u32 *) p3, r, 3);
+ return r;
+}
+
#define CLIB_HAVE_VEC128_MSB_MASK
#define CLIB_HAVE_VEC128_UNALIGNED_LOAD_STORE