diff options
| author |   Nitin Saxena <nsaxena@marvell.com> | 2019-03-28 14:42:31 +0530 |
|---|---|---|
| committer |   Andrew Yourtchenko <ayourtch@gmail.com> | 2019-09-21 09:49:18 +0000 |
| commit | 0dda2a37babda8bcc45a7f180513f92aa2da729e (patch) | |
| tree | c8f2ba66033a518e584e16c562781ff60675c776 /src | |
| parent | c51d2afbb1d5c3b97a899e6841cffbffde118f9e (diff) | |
vppinfra: Update "show cpu" output for AArch64 chips
- Allow "Microarch model(family)" row to show PASS
revison as either string (like A0, B0) or number (like
1.0, 2.0).
- Fix part number for Marvell CN96XX
Type: refactor
Change-Id: Ie01a3960c4e5e481be354dc8bb60f744e5c65737
Signed-off-by: Nitin Saxena <nsaxena@marvell.com>
(cherry picked from commit c9122f97398b11f8be0256901a0cbd83dc3b6511)
Diffstat (limited to 'src')
| -rw-r--r-- | src/vppinfra/cpu.c | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/src/vppinfra/cpu.c b/src/vppinfra/cpu.c index 1b3ac31ef91..c1ff7dd27b3 100644 --- a/src/vppinfra/cpu.c +++ b/src/vppinfra/cpu.c @@ -57,17 +57,18 @@ _(0x06, 0x1a, "Nehalem", "Nehalem EP,Bloomfield)") \ _(0x06, 0x17, "Penryn", "Yorkfield,Wolfdale,Penryn,Harpertown") +/* _(implementor-id, part-id, vendor-name, cpu-name, show CPU pass as string) */ #define foreach_aarch64_cpu_uarch \ - _(0x41, 0xd03, "ARM", "Cortex-A53") \ - _(0x41, 0xd07, "ARM", "Cortex-A57") \ - _(0x41, 0xd08, "ARM", "Cortex-A72") \ - _(0x41, 0xd09, "ARM", "Cortex-A73") \ - _(0x43, 0x0a1, "Cavium", "ThunderX CN88XX") \ - _(0x43, 0x0a2, "Cavium", "Octeon TX CN81XX") \ - _(0x43, 0x0a3, "Cavium", "Octeon TX CN83XX") \ - _(0x43, 0x0af, "Cavium", "ThunderX2 CN99XX") \ - _(0x43, 0x0b1, "Cavium", "Octeon TX2 CN98XX") \ - _(0x43, 0x0b2, "Cavium", "Octeon TX2 CN93XX") \ + _(0x41, 0xd03, "ARM", "Cortex-A53", 0) \ + _(0x41, 0xd07, "ARM", "Cortex-A57", 0) \ + _(0x41, 0xd08, "ARM", "Cortex-A72", 0) \ + _(0x41, 0xd09, "ARM", "Cortex-A73", 0) \ + _(0x43, 0x0a1, "Marvell", "THUNDERX CN88XX", 0) \ + _(0x43, 0x0a2, "Marvell", "OCTEON TX CN81XX", 0) \ + _(0x43, 0x0a3, "Marvell", "OCTEON TX CN83XX", 0) \ + _(0x43, 0x0af, "Marvell", "THUNDERX2 CN99XX", 1) \ + _(0x43, 0x0b1, "Marvell", "OCTEON TX2 CN98XX", 1) \ + _(0x43, 0x0b2, "Marvell", "OCTEON TX2 CN96XX", 1) u8 * format_cpu_uarch (u8 * s, va_list * args) @@ -115,12 +116,14 @@ format(s, "[0x%x] %s ([0x%02x] %s) stepping 0x%x", f, a, m, c, stepping); unformat_free (&input); close (fd); - /* Note: Cavium starts counting variants from 1 instead of 0 */ - if (implementer == 0x43) - variant++; +#define _(i,p,a,c,_format) if ((implementer == i) && (primary_part_number == p)){ \ + if (_format)\ + return format(s, "%s (%s PASS %c%u)", a, c, 'A'+variant, revision);\ + else {\ + if (implementer == 0x43)\ + variant++; \ + return format (s, "%s (%s PASS %u.%u)", a, c, variant, revision);}} -#define _(i,p,a,c) if ((implementer == i) && (primary_part_number == p)) \ - return format(s, "%s (%s PASS %u.%u)", a, c, variant, revision); foreach_aarch64_cpu_uarch #undef _ return format (s, "unknown (implementer 0x%02x part 0x%03x PASS %u.%u)", |